Re: [PATCH v1 16/20] riscv: Add semihosting support
Alistair Francis writes: > Whoops, I thought I had already reviewed this commit. You had provided quite extensive review with lots of useful comments, but never added the magic tag for this commit :-) -- -keith signature.asc Description: PGP signature
Re: [PATCH v1 16/20] riscv: Add semihosting support
On Fri, Jan 8, 2021 at 3:06 PM Alex Bennée wrote: > > From: Keith Packard > > Adapt the arm semihosting support code for RISCV. This implementation > is based on the standard for RISC-V semihosting version 0.2 as > documented in > >https://github.com/riscv/riscv-semihosting-spec/releases/tag/0.2 > > Signed-off-by: Keith Packard > Message-Id: <20210107170717.2098982-6-kei...@keithp.com> > Signed-off-by: Alex Bennée Whoops, I thought I had already reviewed this commit. Reviewed-by: Alistair Francis Alistair > --- > default-configs/devices/riscv32-softmmu.mak | 2 + > default-configs/devices/riscv64-softmmu.mak | 2 + > .../targets/riscv32-linux-user.mak| 1 + > .../targets/riscv64-linux-user.mak| 1 + > hw/semihosting/common-semi.h | 5 +- > linux-user/qemu.h | 4 +- > target/riscv/cpu_bits.h | 1 + > hw/semihosting/common-semi.c | 82 ++- > linux-user/semihost.c | 8 +- > target/riscv/cpu_helper.c | 10 +++ > target/riscv/translate.c | 11 +++ > .../riscv/insn_trans/trans_privileged.c.inc | 37 - > qemu-options.hx | 10 ++- > 13 files changed, 162 insertions(+), 12 deletions(-) > > diff --git a/default-configs/devices/riscv32-softmmu.mak > b/default-configs/devices/riscv32-softmmu.mak > index 94a236c9c2..d847bd5692 100644 > --- a/default-configs/devices/riscv32-softmmu.mak > +++ b/default-configs/devices/riscv32-softmmu.mak > @@ -3,6 +3,8 @@ > # Uncomment the following lines to disable these optional devices: > # > #CONFIG_PCI_DEVICES=n > +CONFIG_SEMIHOSTING=y > +CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y > > # Boards: > # > diff --git a/default-configs/devices/riscv64-softmmu.mak > b/default-configs/devices/riscv64-softmmu.mak > index 76b6195648..d5eec75f05 100644 > --- a/default-configs/devices/riscv64-softmmu.mak > +++ b/default-configs/devices/riscv64-softmmu.mak > @@ -3,6 +3,8 @@ > # Uncomment the following lines to disable these optional devices: > # > #CONFIG_PCI_DEVICES=n > +CONFIG_SEMIHOSTING=y > +CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y > > # Boards: > # > diff --git a/default-configs/targets/riscv32-linux-user.mak > b/default-configs/targets/riscv32-linux-user.mak > index dfb259e8aa..6a9d1b1bc1 100644 > --- a/default-configs/targets/riscv32-linux-user.mak > +++ b/default-configs/targets/riscv32-linux-user.mak > @@ -2,3 +2,4 @@ TARGET_ARCH=riscv32 > TARGET_BASE_ARCH=riscv > TARGET_ABI_DIR=riscv > TARGET_XML_FILES= gdb-xml/riscv-32bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml > gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-32bit-csr.xml > gdb-xml/riscv-32bit-virtual.xml > +CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y > diff --git a/default-configs/targets/riscv64-linux-user.mak > b/default-configs/targets/riscv64-linux-user.mak > index b13895f3b0..0a92849a1b 100644 > --- a/default-configs/targets/riscv64-linux-user.mak > +++ b/default-configs/targets/riscv64-linux-user.mak > @@ -2,3 +2,4 @@ TARGET_ARCH=riscv64 > TARGET_BASE_ARCH=riscv > TARGET_ABI_DIR=riscv > TARGET_XML_FILES= gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml > gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-64bit-csr.xml > gdb-xml/riscv-64bit-virtual.xml > +CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y > diff --git a/hw/semihosting/common-semi.h b/hw/semihosting/common-semi.h > index bc53e92c79..0bfab1c669 100644 > --- a/hw/semihosting/common-semi.h > +++ b/hw/semihosting/common-semi.h > @@ -1,6 +1,6 @@ > /* > * Semihosting support for systems modeled on the Arm "Angel" > - * semihosting syscalls design. > + * semihosting syscalls design. This includes Arm and RISC-V processors > * > * Copyright (c) 2005, 2007 CodeSourcery. > * Copyright (c) 2019 Linaro > @@ -26,6 +26,9 @@ > * Semihosting for AArch32 and AArch64 Release 2.0 > * https://static.docs.arm.com/100863/0200/semihosting.pdf > * > + * RISC-V Semihosting is documented in: > + * RISC-V Semihosting > + * > https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc > */ > > #ifndef COMMON_SEMI_H > diff --git a/linux-user/qemu.h b/linux-user/qemu.h > index 534753ca12..17aa992165 100644 > --- a/linux-user/qemu.h > +++ b/linux-user/qemu.h > @@ -109,6 +109,8 @@ typedef struct TaskState { > /* FPA state */ > FPA11 fpa; > # endif > +#endif > +#if defined(TARGET_ARM) || defined(TARGET_RISCV) > int swi_errno; > #endif > #if defined(TARGET_I386) && !defined(TARGET_X86_64) > @@ -122,7 +124,7 @@ typedef struct TaskState { > #ifdef TARGET_M68K > abi_ulong tp_value; > #endif > -#if defined(TARGET_ARM) || defined(TARGET_M68K) > +#if defined(TARGET_ARM) || defined(TARGET_M68K) || defined(TARGET_RISCV) > /* Extra fields for semihosted binaries. */ > abi_ulong heap_base; > abi_ulong heap_limit; > diff --git a/target/riscv/cpu_bits.h
[PATCH v1 16/20] riscv: Add semihosting support
From: Keith Packard Adapt the arm semihosting support code for RISCV. This implementation is based on the standard for RISC-V semihosting version 0.2 as documented in https://github.com/riscv/riscv-semihosting-spec/releases/tag/0.2 Signed-off-by: Keith Packard Message-Id: <20210107170717.2098982-6-kei...@keithp.com> Signed-off-by: Alex Bennée --- default-configs/devices/riscv32-softmmu.mak | 2 + default-configs/devices/riscv64-softmmu.mak | 2 + .../targets/riscv32-linux-user.mak| 1 + .../targets/riscv64-linux-user.mak| 1 + hw/semihosting/common-semi.h | 5 +- linux-user/qemu.h | 4 +- target/riscv/cpu_bits.h | 1 + hw/semihosting/common-semi.c | 82 ++- linux-user/semihost.c | 8 +- target/riscv/cpu_helper.c | 10 +++ target/riscv/translate.c | 11 +++ .../riscv/insn_trans/trans_privileged.c.inc | 37 - qemu-options.hx | 10 ++- 13 files changed, 162 insertions(+), 12 deletions(-) diff --git a/default-configs/devices/riscv32-softmmu.mak b/default-configs/devices/riscv32-softmmu.mak index 94a236c9c2..d847bd5692 100644 --- a/default-configs/devices/riscv32-softmmu.mak +++ b/default-configs/devices/riscv32-softmmu.mak @@ -3,6 +3,8 @@ # Uncomment the following lines to disable these optional devices: # #CONFIG_PCI_DEVICES=n +CONFIG_SEMIHOSTING=y +CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y # Boards: # diff --git a/default-configs/devices/riscv64-softmmu.mak b/default-configs/devices/riscv64-softmmu.mak index 76b6195648..d5eec75f05 100644 --- a/default-configs/devices/riscv64-softmmu.mak +++ b/default-configs/devices/riscv64-softmmu.mak @@ -3,6 +3,8 @@ # Uncomment the following lines to disable these optional devices: # #CONFIG_PCI_DEVICES=n +CONFIG_SEMIHOSTING=y +CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y # Boards: # diff --git a/default-configs/targets/riscv32-linux-user.mak b/default-configs/targets/riscv32-linux-user.mak index dfb259e8aa..6a9d1b1bc1 100644 --- a/default-configs/targets/riscv32-linux-user.mak +++ b/default-configs/targets/riscv32-linux-user.mak @@ -2,3 +2,4 @@ TARGET_ARCH=riscv32 TARGET_BASE_ARCH=riscv TARGET_ABI_DIR=riscv TARGET_XML_FILES= gdb-xml/riscv-32bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-32bit-csr.xml gdb-xml/riscv-32bit-virtual.xml +CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y diff --git a/default-configs/targets/riscv64-linux-user.mak b/default-configs/targets/riscv64-linux-user.mak index b13895f3b0..0a92849a1b 100644 --- a/default-configs/targets/riscv64-linux-user.mak +++ b/default-configs/targets/riscv64-linux-user.mak @@ -2,3 +2,4 @@ TARGET_ARCH=riscv64 TARGET_BASE_ARCH=riscv TARGET_ABI_DIR=riscv TARGET_XML_FILES= gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-64bit-csr.xml gdb-xml/riscv-64bit-virtual.xml +CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y diff --git a/hw/semihosting/common-semi.h b/hw/semihosting/common-semi.h index bc53e92c79..0bfab1c669 100644 --- a/hw/semihosting/common-semi.h +++ b/hw/semihosting/common-semi.h @@ -1,6 +1,6 @@ /* * Semihosting support for systems modeled on the Arm "Angel" - * semihosting syscalls design. + * semihosting syscalls design. This includes Arm and RISC-V processors * * Copyright (c) 2005, 2007 CodeSourcery. * Copyright (c) 2019 Linaro @@ -26,6 +26,9 @@ * Semihosting for AArch32 and AArch64 Release 2.0 * https://static.docs.arm.com/100863/0200/semihosting.pdf * + * RISC-V Semihosting is documented in: + * RISC-V Semihosting + * https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc */ #ifndef COMMON_SEMI_H diff --git a/linux-user/qemu.h b/linux-user/qemu.h index 534753ca12..17aa992165 100644 --- a/linux-user/qemu.h +++ b/linux-user/qemu.h @@ -109,6 +109,8 @@ typedef struct TaskState { /* FPA state */ FPA11 fpa; # endif +#endif +#if defined(TARGET_ARM) || defined(TARGET_RISCV) int swi_errno; #endif #if defined(TARGET_I386) && !defined(TARGET_X86_64) @@ -122,7 +124,7 @@ typedef struct TaskState { #ifdef TARGET_M68K abi_ulong tp_value; #endif -#if defined(TARGET_ARM) || defined(TARGET_M68K) +#if defined(TARGET_ARM) || defined(TARGET_M68K) || defined(TARGET_RISCV) /* Extra fields for semihosted binaries. */ abi_ulong heap_base; abi_ulong heap_limit; diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index b41e8836c3..4196ef8b69 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -542,6 +542,7 @@ #define RISCV_EXCP_INST_PAGE_FAULT 0xc /* since: priv-1.10.0 */ #define RISCV_EXCP_LOAD_PAGE_FAULT 0xd /* since: priv-1.10.0 */ #define RISCV_EXCP_STORE_PAGE_FAULT 0xf /* since: priv-1.10.0 */ +#define RISCV_EXCP_SEMIHOST