Re: [PATCH 24/25] arm: Remove frq properties on CMSDK timer, dualtimer, watchdog, ARMSSE

2021-01-23 Thread Luc Michel
On 19:06 Thu 21 Jan , Peter Maydell wrote:
> Now no users are setting the frq properties on the CMSDK timer,
> dualtimer, watchdog or ARMSSE SoC devices, we can remove the
> properties and the struct fields that back them.
> 
> Signed-off-by: Peter Maydell 

Reviewed-by: Luc Michel 

> ---
>  include/hw/arm/armsse.h  | 2 --
>  include/hw/timer/cmsdk-apb-dualtimer.h   | 2 --
>  include/hw/timer/cmsdk-apb-timer.h   | 2 --
>  include/hw/watchdog/cmsdk-apb-watchdog.h | 2 --
>  hw/arm/armsse.c  | 2 --
>  hw/timer/cmsdk-apb-dualtimer.c   | 6 --
>  hw/timer/cmsdk-apb-timer.c   | 6 --
>  hw/watchdog/cmsdk-apb-watchdog.c | 6 --
>  8 files changed, 28 deletions(-)
> 
> diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h
> index bfa1e79c4fe..676cd4f36b0 100644
> --- a/include/hw/arm/armsse.h
> +++ b/include/hw/arm/armsse.h
> @@ -41,7 +41,6 @@
>   *  + Clock input "S32KCLK": slow 32KHz clock used for a few peripherals
>   *  + QOM property "memory" is a MemoryRegion containing the devices provided
>   *by the board model.
> - *  + QOM property "MAINCLK_FRQ" is the frequency of the main system clock
>   *  + QOM property "EXP_NUMIRQ" sets the number of expansion interrupts.
>   *(In hardware, the SSE-200 permits the number of expansion interrupts
>   *for the two CPUs to be configured separately, but we restrict it to
> @@ -218,7 +217,6 @@ struct ARMSSE {
>  /* Properties */
>  MemoryRegion *board_memory;
>  uint32_t exp_numirq;
> -uint32_t mainclk_frq;
>  uint32_t sram_addr_width;
>  uint32_t init_svtor;
>  bool cpu_fpu[SSE_MAX_CPUS];
> diff --git a/include/hw/timer/cmsdk-apb-dualtimer.h 
> b/include/hw/timer/cmsdk-apb-dualtimer.h
> index 3adbb01dd34..f3ec86c00b5 100644
> --- a/include/hw/timer/cmsdk-apb-dualtimer.h
> +++ b/include/hw/timer/cmsdk-apb-dualtimer.h
> @@ -16,7 +16,6 @@
>   * 
> https://developer.arm.com/products/system-design/system-design-kits/cortex-m-system-design-kit
>   *
>   * QEMU interface:
> - *  + QOM property "pclk-frq": frequency at which the timer is clocked
>   *  + Clock input "TIMCLK": clock (for both timers)
>   *  + sysbus MMIO region 0: the register bank
>   *  + sysbus IRQ 0: combined timer interrupt TIMINTC
> @@ -63,7 +62,6 @@ struct CMSDKAPBDualTimer {
>  /*< public >*/
>  MemoryRegion iomem;
>  qemu_irq timerintc;
> -uint32_t pclk_frq;
>  Clock *timclk;
>  
>  CMSDKAPBDualTimerModule timermod[CMSDK_APB_DUALTIMER_NUM_MODULES];
> diff --git a/include/hw/timer/cmsdk-apb-timer.h 
> b/include/hw/timer/cmsdk-apb-timer.h
> index 54f7ec8c502..c4c7eae8499 100644
> --- a/include/hw/timer/cmsdk-apb-timer.h
> +++ b/include/hw/timer/cmsdk-apb-timer.h
> @@ -23,7 +23,6 @@ OBJECT_DECLARE_SIMPLE_TYPE(CMSDKAPBTimer, CMSDK_APB_TIMER)
>  
>  /*
>   * QEMU interface:
> - *  + QOM property "pclk-frq": frequency at which the timer is clocked
>   *  + Clock input "pclk": clock for the timer
>   *  + sysbus MMIO region 0: the register bank
>   *  + sysbus IRQ 0: timer interrupt TIMERINT
> @@ -35,7 +34,6 @@ struct CMSDKAPBTimer {
>  /*< public >*/
>  MemoryRegion iomem;
>  qemu_irq timerint;
> -uint32_t pclk_frq;
>  struct ptimer_state *timer;
>  Clock *pclk;
>  
> diff --git a/include/hw/watchdog/cmsdk-apb-watchdog.h 
> b/include/hw/watchdog/cmsdk-apb-watchdog.h
> index 34069ca6969..c6b3e78731e 100644
> --- a/include/hw/watchdog/cmsdk-apb-watchdog.h
> +++ b/include/hw/watchdog/cmsdk-apb-watchdog.h
> @@ -16,7 +16,6 @@
>   * 
> https://developer.arm.com/products/system-design/system-design-kits/cortex-m-system-design-kit
>   *
>   * QEMU interface:
> - *  + QOM property "wdogclk-frq": frequency at which the watchdog is clocked
>   *  + Clock input "WDOGCLK": clock for the watchdog's timer
>   *  + sysbus MMIO region 0: the register bank
>   *  + sysbus IRQ 0: watchdog interrupt
> @@ -53,7 +52,6 @@ struct CMSDKAPBWatchdog {
>  /*< public >*/
>  MemoryRegion iomem;
>  qemu_irq wdogint;
> -uint32_t wdogclk_frq;
>  bool is_luminary;
>  struct ptimer_state *timer;
>  Clock *wdogclk;
> diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
> index 7494afc630e..513caa33a9a 100644
> --- a/hw/arm/armsse.c
> +++ b/hw/arm/armsse.c
> @@ -48,7 +48,6 @@ static Property iotkit_properties[] = {
>  DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION,
>   MemoryRegion *),
>  DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64),
> -DEFINE_PROP_UINT32("MAINCLK_FRQ", ARMSSE, mainclk_frq, 0),
>  DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15),
>  DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x1000),
>  DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true),
> @@ -60,7 +59,6 @@ static Property armsse_properties[] = {
>  DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION,
>   MemoryRegion *),
>  

Re: [PATCH 24/25] arm: Remove frq properties on CMSDK timer, dualtimer, watchdog, ARMSSE

2021-01-21 Thread Philippe Mathieu-Daudé
On 1/21/21 8:06 PM, Peter Maydell wrote:
> Now no users are setting the frq properties on the CMSDK timer,

"Now that no ..."? No clue, double "no*" sounds odd to me :)

> dualtimer, watchdog or ARMSSE SoC devices, we can remove the
> properties and the struct fields that back them.
> 
> Signed-off-by: Peter Maydell 
> ---
>  include/hw/arm/armsse.h  | 2 --
>  include/hw/timer/cmsdk-apb-dualtimer.h   | 2 --
>  include/hw/timer/cmsdk-apb-timer.h   | 2 --
>  include/hw/watchdog/cmsdk-apb-watchdog.h | 2 --
>  hw/arm/armsse.c  | 2 --
>  hw/timer/cmsdk-apb-dualtimer.c   | 6 --
>  hw/timer/cmsdk-apb-timer.c   | 6 --
>  hw/watchdog/cmsdk-apb-watchdog.c | 6 --
>  8 files changed, 28 deletions(-)

Reviewed-by: Philippe Mathieu-Daudé 



[PATCH 24/25] arm: Remove frq properties on CMSDK timer, dualtimer, watchdog, ARMSSE

2021-01-21 Thread Peter Maydell
Now no users are setting the frq properties on the CMSDK timer,
dualtimer, watchdog or ARMSSE SoC devices, we can remove the
properties and the struct fields that back them.

Signed-off-by: Peter Maydell 
---
 include/hw/arm/armsse.h  | 2 --
 include/hw/timer/cmsdk-apb-dualtimer.h   | 2 --
 include/hw/timer/cmsdk-apb-timer.h   | 2 --
 include/hw/watchdog/cmsdk-apb-watchdog.h | 2 --
 hw/arm/armsse.c  | 2 --
 hw/timer/cmsdk-apb-dualtimer.c   | 6 --
 hw/timer/cmsdk-apb-timer.c   | 6 --
 hw/watchdog/cmsdk-apb-watchdog.c | 6 --
 8 files changed, 28 deletions(-)

diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h
index bfa1e79c4fe..676cd4f36b0 100644
--- a/include/hw/arm/armsse.h
+++ b/include/hw/arm/armsse.h
@@ -41,7 +41,6 @@
  *  + Clock input "S32KCLK": slow 32KHz clock used for a few peripherals
  *  + QOM property "memory" is a MemoryRegion containing the devices provided
  *by the board model.
- *  + QOM property "MAINCLK_FRQ" is the frequency of the main system clock
  *  + QOM property "EXP_NUMIRQ" sets the number of expansion interrupts.
  *(In hardware, the SSE-200 permits the number of expansion interrupts
  *for the two CPUs to be configured separately, but we restrict it to
@@ -218,7 +217,6 @@ struct ARMSSE {
 /* Properties */
 MemoryRegion *board_memory;
 uint32_t exp_numirq;
-uint32_t mainclk_frq;
 uint32_t sram_addr_width;
 uint32_t init_svtor;
 bool cpu_fpu[SSE_MAX_CPUS];
diff --git a/include/hw/timer/cmsdk-apb-dualtimer.h 
b/include/hw/timer/cmsdk-apb-dualtimer.h
index 3adbb01dd34..f3ec86c00b5 100644
--- a/include/hw/timer/cmsdk-apb-dualtimer.h
+++ b/include/hw/timer/cmsdk-apb-dualtimer.h
@@ -16,7 +16,6 @@
  * 
https://developer.arm.com/products/system-design/system-design-kits/cortex-m-system-design-kit
  *
  * QEMU interface:
- *  + QOM property "pclk-frq": frequency at which the timer is clocked
  *  + Clock input "TIMCLK": clock (for both timers)
  *  + sysbus MMIO region 0: the register bank
  *  + sysbus IRQ 0: combined timer interrupt TIMINTC
@@ -63,7 +62,6 @@ struct CMSDKAPBDualTimer {
 /*< public >*/
 MemoryRegion iomem;
 qemu_irq timerintc;
-uint32_t pclk_frq;
 Clock *timclk;
 
 CMSDKAPBDualTimerModule timermod[CMSDK_APB_DUALTIMER_NUM_MODULES];
diff --git a/include/hw/timer/cmsdk-apb-timer.h 
b/include/hw/timer/cmsdk-apb-timer.h
index 54f7ec8c502..c4c7eae8499 100644
--- a/include/hw/timer/cmsdk-apb-timer.h
+++ b/include/hw/timer/cmsdk-apb-timer.h
@@ -23,7 +23,6 @@ OBJECT_DECLARE_SIMPLE_TYPE(CMSDKAPBTimer, CMSDK_APB_TIMER)
 
 /*
  * QEMU interface:
- *  + QOM property "pclk-frq": frequency at which the timer is clocked
  *  + Clock input "pclk": clock for the timer
  *  + sysbus MMIO region 0: the register bank
  *  + sysbus IRQ 0: timer interrupt TIMERINT
@@ -35,7 +34,6 @@ struct CMSDKAPBTimer {
 /*< public >*/
 MemoryRegion iomem;
 qemu_irq timerint;
-uint32_t pclk_frq;
 struct ptimer_state *timer;
 Clock *pclk;
 
diff --git a/include/hw/watchdog/cmsdk-apb-watchdog.h 
b/include/hw/watchdog/cmsdk-apb-watchdog.h
index 34069ca6969..c6b3e78731e 100644
--- a/include/hw/watchdog/cmsdk-apb-watchdog.h
+++ b/include/hw/watchdog/cmsdk-apb-watchdog.h
@@ -16,7 +16,6 @@
  * 
https://developer.arm.com/products/system-design/system-design-kits/cortex-m-system-design-kit
  *
  * QEMU interface:
- *  + QOM property "wdogclk-frq": frequency at which the watchdog is clocked
  *  + Clock input "WDOGCLK": clock for the watchdog's timer
  *  + sysbus MMIO region 0: the register bank
  *  + sysbus IRQ 0: watchdog interrupt
@@ -53,7 +52,6 @@ struct CMSDKAPBWatchdog {
 /*< public >*/
 MemoryRegion iomem;
 qemu_irq wdogint;
-uint32_t wdogclk_frq;
 bool is_luminary;
 struct ptimer_state *timer;
 Clock *wdogclk;
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
index 7494afc630e..513caa33a9a 100644
--- a/hw/arm/armsse.c
+++ b/hw/arm/armsse.c
@@ -48,7 +48,6 @@ static Property iotkit_properties[] = {
 DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION,
  MemoryRegion *),
 DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64),
-DEFINE_PROP_UINT32("MAINCLK_FRQ", ARMSSE, mainclk_frq, 0),
 DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15),
 DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x1000),
 DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true),
@@ -60,7 +59,6 @@ static Property armsse_properties[] = {
 DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION,
  MemoryRegion *),
 DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64),
-DEFINE_PROP_UINT32("MAINCLK_FRQ", ARMSSE, mainclk_frq, 0),
 DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15),
 DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x1000),
 DEFINE_PROP_BOOL("CPU0_FPU",