Re: [Qemu-devel] [PATCH, MIPS64] Fix Status_rw_bitmask values
Thiemo Seufer a écrit : Aurelien Jarno wrote: Hi all, The patch below fixes the Status_rw_bitmask values for 64-bit CPUs: - Reverse endianess is currently not implemented, the RE bit should not be writable. OTOH, those CPUs support RE, that's why I left the bit writable. I think you'll have to boot RiscOS to check the difference, I don't know of any other user. :-) Ok, I see. The best would clearly to implement that. - 64-bit is implemented, the PX bit should be writable. The current version is correct, R4000 and 5K don't implement PX, the 20Kc and later CPUs do. I don't know about R4000, but the 5K manual (from www.mips.com) clearly says that this bit is implemented. Also this bit is marked as required in the MIPS64 PRA manual (for both R1 and R2), and the 5K CPU is presented as a MIPS64R1 CPU. -- .''`. Aurelien Jarno | GPG: 1024D/F1BCDB73 : :' : Debian developer | Electrical Engineer `. `' [EMAIL PROTECTED] | [EMAIL PROTECTED] `-people.debian.org/~aurel32 | www.aurel32.net
Re: [Qemu-devel] [PATCH, MIPS64] Fix Status_rw_bitmask values
Aurelien Jarno wrote: [snip] - 64-bit is implemented, the PX bit should be writable. The current version is correct, R4000 and 5K don't implement PX, the 20Kc and later CPUs do. I don't know about R4000, but the 5K manual (from www.mips.com) clearly says that this bit is implemented. Also this bit is marked as required in the MIPS64 PRA manual (for both R1 and R2), and the 5K CPU is presented as a MIPS64R1 CPU. Agreed for the 5K, I used too old Documentation to check this. Thiemo
Re: [Qemu-devel] [PATCH, MIPS64] Fix Status_rw_bitmask values
Aurelien Jarno wrote: Hi all, The patch below fixes the Status_rw_bitmask values for 64-bit CPUs: - Reverse endianess is currently not implemented, the RE bit should not be writable. OTOH, those CPUs support RE, that's why I left the bit writable. I think you'll have to boot RiscOS to check the difference, I don't know of any other user. :-) - 64-bit is implemented, the PX bit should be writable. The current version is correct, R4000 and 5K don't implement PX, the 20Kc and later CPUs do. Thiemo
[Qemu-devel] [PATCH, MIPS64] Fix Status_rw_bitmask values
Hi all,
The patch below fixes the Status_rw_bitmask values for 64-bit CPUs:
- Reverse endianess is currently not implemented, the RE bit should
not be writable.
- 64-bit is implemented, the PX bit should be writable.
Bye,
Aurelien
Index: target-mips/translate_init.c
===
RCS file: /sources/qemu/qemu/target-mips/translate_init.c,v
retrieving revision 1.13
diff -u -d -p -r1.13 translate_init.c
--- target-mips/translate_init.c1 Jun 2007 21:57:32 - 1.13
+++ target-mips/translate_init.c4 Jun 2007 13:00:30 -
@@ -145,7 +145,7 @@ static mips_def_t mips_defs[] =
.CP0_Config3 = MIPS_CONFIG3,
.SYNCI_Step = 16,
.CCRes = 2,
-.Status_rw_bitmask = 0x3678,
+.Status_rw_bitmask = 0x34F8,
/* The R4000 has a full 64bit FPU doesn't use the fcr0 bits. */
.CP1_fcr0 = (0x5 FCR0_PRID) | (0x0 FCR0_REV),
},
@@ -161,7 +161,7 @@ static mips_def_t mips_defs[] =
.CP0_Config3 = MIPS_CONFIG3,
.SYNCI_Step = 32,
.CCRes = 2,
-.Status_rw_bitmask = 0x3278,
+.Status_rw_bitmask = 0x30F8,
},
{
.name = 5Kf,
@@ -175,7 +175,7 @@ static mips_def_t mips_defs[] =
.CP0_Config3 = MIPS_CONFIG3,
.SYNCI_Step = 32,
.CCRes = 2,
-.Status_rw_bitmask = 0x3678,
+.Status_rw_bitmask = 0x34F8,
/* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */
.CP1_fcr0 = (1 FCR0_D) | (1 FCR0_S) |
(0x81 FCR0_PRID) | (0x0 FCR0_REV),
@@ -192,7 +192,7 @@ static mips_def_t mips_defs[] =
.CP0_Config3 = MIPS_CONFIG3,
.SYNCI_Step = 32,
.CCRes = 2,
-.Status_rw_bitmask = 0x36FB,
+.Status_rw_bitmask = 0x34FB,
/* The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */
.CP1_fcr0 = (1 FCR0_3D) | (1 FCR0_PS) |
(1 FCR0_D) | (1 FCR0_S) |
--
.''`. Aurelien Jarno | GPG: 1024D/F1BCDB73
: :' : Debian developer | Electrical Engineer
`. `' [EMAIL PROTECTED] | [EMAIL PROTECTED]
`-people.debian.org/~aurel32 | www.aurel32.net
