Re: [Qemu-devel] [PATCH for 4.0 v2 2/2] riscv: plic: Log guest errors
On Wed, 27 Mar 2019 11:52:53 PDT (-0700), alistai...@gmail.com wrote: On Wed, Mar 27, 2019 at 11:51 AM Alistair Francis wrote: Instead of using error_report() to print guest errors let's use qemu_log_mask(LOG_GUEST_ERROR,...) to log the error. Signed-off-by: Alistair Francis I dropped Philippe's review in this series. This should be included from v1: Reviewed-by: Philippe Mathieu-Daudé I got it. Alistair --- hw/riscv/sifive_plic.c | 12 +--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c index 70a85cd075..7f373d6c9d 100644 --- a/hw/riscv/sifive_plic.c +++ b/hw/riscv/sifive_plic.c @@ -262,7 +262,9 @@ static uint64_t sifive_plic_read(void *opaque, hwaddr addr, unsigned size) } err: -error_report("plic: invalid register read: %08x", (uint32_t)addr); +qemu_log_mask(LOG_GUEST_ERROR, + "%s: Invalid register read 0x%" HWADDR_PRIx "\n", + __func__, addr); return 0; } @@ -289,7 +291,9 @@ static void sifive_plic_write(void *opaque, hwaddr addr, uint64_t value, } else if (addr >= plic->pending_base && /* 1 bit per source */ addr < plic->pending_base + (plic->num_sources >> 3)) { -error_report("plic: invalid pending write: %08x", (uint32_t)addr); +qemu_log_mask(LOG_GUEST_ERROR, + "%s: invalid pending write: 0x%" HWADDR_PRIx "", + __func__, addr); return; } else if (addr >= plic->enable_base && /* 1 bit per source */ addr < plic->enable_base + plic->num_addrs * plic->enable_stride) @@ -339,7 +343,9 @@ static void sifive_plic_write(void *opaque, hwaddr addr, uint64_t value, } err: -error_report("plic: invalid register write: %08x", (uint32_t)addr); +qemu_log_mask(LOG_GUEST_ERROR, + "%s: Invalid register write 0x%" HWADDR_PRIx "\n", + __func__, addr); } static const MemoryRegionOps sifive_plic_ops = { -- 2.21.0
Re: [Qemu-devel] [PATCH for 4.0 v2 2/2] riscv: plic: Log guest errors
Le mer. 27 mars 2019 19:57, Alistair Francis a écrit : > Instead of using error_report() to print guest errors let's use > qemu_log_mask(LOG_GUEST_ERROR,...) to log the error. > > Signed-off-by: Alistair Francis > --- > hw/riscv/sifive_plic.c | 12 +--- > 1 file changed, 9 insertions(+), 3 deletions(-) > > diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c > index 70a85cd075..7f373d6c9d 100644 > --- a/hw/riscv/sifive_plic.c > +++ b/hw/riscv/sifive_plic.c > @@ -262,7 +262,9 @@ static uint64_t sifive_plic_read(void *opaque, hwaddr > addr, unsigned size) > } > > err: > -error_report("plic: invalid register read: %08x", (uint32_t)addr); > +qemu_log_mask(LOG_GUEST_ERROR, > + "%s: Invalid register read 0x%" HWADDR_PRIx "\n", > + __func__, addr); > return 0; > } > > @@ -289,7 +291,9 @@ static void sifive_plic_write(void *opaque, hwaddr > addr, uint64_t value, > } else if (addr >= plic->pending_base && /* 1 bit per source */ > addr < plic->pending_base + (plic->num_sources >> 3)) > { > -error_report("plic: invalid pending write: %08x", (uint32_t)addr); > +qemu_log_mask(LOG_GUEST_ERROR, > + "%s: invalid pending write: 0x%" HWADDR_PRIx "", > + __func__, addr); > return; > } else if (addr >= plic->enable_base && /* 1 bit per source */ > addr < plic->enable_base + plic->num_addrs * plic->enable_stride) > @@ -339,7 +343,9 @@ static void sifive_plic_write(void *opaque, hwaddr > addr, uint64_t value, > } > > err: > -error_report("plic: invalid register write: %08x", (uint32_t)addr); > +qemu_log_mask(LOG_GUEST_ERROR, > + "%s: Invalid register write 0x%" HWADDR_PRIx "\n", > + __func__, addr); > } > > static const MemoryRegionOps sifive_plic_ops = { > -- > 2.21.0 > I'm using the GMail embedded gapp and wonder if the deduplication features is not sometimes abusive, when the same patch is sent increasing versions, I reply to the last version I see but my reply looks like I replied to the first. I might be also misusing the gapp :) Anyway: Reviewed-by: Philippe Mathieu-Daudé >
[Qemu-devel] [PATCH for 4.0 v2 2/2] riscv: plic: Log guest errors
Instead of using error_report() to print guest errors let's use qemu_log_mask(LOG_GUEST_ERROR,...) to log the error. Signed-off-by: Alistair Francis --- hw/riscv/sifive_plic.c | 12 +--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c index 70a85cd075..7f373d6c9d 100644 --- a/hw/riscv/sifive_plic.c +++ b/hw/riscv/sifive_plic.c @@ -262,7 +262,9 @@ static uint64_t sifive_plic_read(void *opaque, hwaddr addr, unsigned size) } err: -error_report("plic: invalid register read: %08x", (uint32_t)addr); +qemu_log_mask(LOG_GUEST_ERROR, + "%s: Invalid register read 0x%" HWADDR_PRIx "\n", + __func__, addr); return 0; } @@ -289,7 +291,9 @@ static void sifive_plic_write(void *opaque, hwaddr addr, uint64_t value, } else if (addr >= plic->pending_base && /* 1 bit per source */ addr < plic->pending_base + (plic->num_sources >> 3)) { -error_report("plic: invalid pending write: %08x", (uint32_t)addr); +qemu_log_mask(LOG_GUEST_ERROR, + "%s: invalid pending write: 0x%" HWADDR_PRIx "", + __func__, addr); return; } else if (addr >= plic->enable_base && /* 1 bit per source */ addr < plic->enable_base + plic->num_addrs * plic->enable_stride) @@ -339,7 +343,9 @@ static void sifive_plic_write(void *opaque, hwaddr addr, uint64_t value, } err: -error_report("plic: invalid register write: %08x", (uint32_t)addr); +qemu_log_mask(LOG_GUEST_ERROR, + "%s: Invalid register write 0x%" HWADDR_PRIx "\n", + __func__, addr); } static const MemoryRegionOps sifive_plic_ops = { -- 2.21.0
Re: [Qemu-devel] [PATCH for 4.0 v2 2/2] riscv: plic: Log guest errors
On Wed, Mar 27, 2019 at 11:51 AM Alistair Francis wrote: > > Instead of using error_report() to print guest errors let's use > qemu_log_mask(LOG_GUEST_ERROR,...) to log the error. > > Signed-off-by: Alistair Francis I dropped Philippe's review in this series. This should be included from v1: Reviewed-by: Philippe Mathieu-Daudé Alistair > --- > hw/riscv/sifive_plic.c | 12 +--- > 1 file changed, 9 insertions(+), 3 deletions(-) > > diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c > index 70a85cd075..7f373d6c9d 100644 > --- a/hw/riscv/sifive_plic.c > +++ b/hw/riscv/sifive_plic.c > @@ -262,7 +262,9 @@ static uint64_t sifive_plic_read(void *opaque, hwaddr > addr, unsigned size) > } > > err: > -error_report("plic: invalid register read: %08x", (uint32_t)addr); > +qemu_log_mask(LOG_GUEST_ERROR, > + "%s: Invalid register read 0x%" HWADDR_PRIx "\n", > + __func__, addr); > return 0; > } > > @@ -289,7 +291,9 @@ static void sifive_plic_write(void *opaque, hwaddr addr, > uint64_t value, > } else if (addr >= plic->pending_base && /* 1 bit per source */ > addr < plic->pending_base + (plic->num_sources >> 3)) > { > -error_report("plic: invalid pending write: %08x", (uint32_t)addr); > +qemu_log_mask(LOG_GUEST_ERROR, > + "%s: invalid pending write: 0x%" HWADDR_PRIx "", > + __func__, addr); > return; > } else if (addr >= plic->enable_base && /* 1 bit per source */ > addr < plic->enable_base + plic->num_addrs * plic->enable_stride) > @@ -339,7 +343,9 @@ static void sifive_plic_write(void *opaque, hwaddr addr, > uint64_t value, > } > > err: > -error_report("plic: invalid register write: %08x", (uint32_t)addr); > +qemu_log_mask(LOG_GUEST_ERROR, > + "%s: Invalid register write 0x%" HWADDR_PRIx "\n", > + __func__, addr); > } > > static const MemoryRegionOps sifive_plic_ops = { > -- > 2.21.0 >