Re: [Qemu-devel] [PATCH v1 07/22] RISC-V: Remove unused class definitions from

2018-03-06 Thread Michael Clark 
On Wed, Mar 7, 2018 at 5:14 PM, Michael Clark  wrote:

>
>
> On Wed, Mar 7, 2018 at 12:27 PM, Philippe Mathieu-Daudé 
> wrote:
>
>>
>> Ok until here.
>>
>> > diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h
>> > index 0aebc57..818fbdc 100644
>> > --- a/include/hw/riscv/sifive_e.h
>> > +++ b/include/hw/riscv/sifive_e.h
>> > @@ -19,16 +19,7 @@
>> >  #ifndef HW_SIFIVE_E_H
>> >  #define HW_SIFIVE_E_H
>> >
>> > -#define TYPE_SIFIVE_E "riscv.sifive_e"
>> > -
>> > -#define SIFIVE_E(obj) \
>> > -OBJECT_CHECK(SiFiveEState, (obj), TYPE_SIFIVE_E)
>> > -
>> >  typedef struct SiFiveEState {
>> > -/*< private >*/
>> > -SysBusDevice parent_obj;
>>
>> I'd keep however a 'Object parent_obj' here, to stay QOM; but your patch
>> is valid.
>>
>
> Okay I'll keep parent_obj when I respin.
>

BTW is the string constant in DEFINE_MACHINE a QOM type?

i.e. should I keep the type conversion and type name macros and use the
type name macro in DEFINE_MACHINE?

Re: [Qemu-devel] [PATCH v1 07/22] RISC-V: Remove unused class definitions from

2018-03-06 Thread Michael Clark 
On Wed, Mar 7, 2018 at 12:27 PM, Philippe Mathieu-Daudé 
wrote:

> Hi Michael,
>
> On 03/06/2018 05:43 PM, Michael Clark wrote:
> > Removes a whole lot of unnecessary boilerplate code. Machines
> > don't need to be objects. The expansion of the SOC object model
> > for the RISC-V machines will happen in the future as SiFive
> > plans to add their FE310 and FU540 SOCs to QEMU. However, it
> > seems that this present boilerplate is complete unnecessary.
> >
> > Signed-off-by: Michael Clark 
> > Signed-off-by: Palmer Dabbelt 
> > ---
> >  hw/riscv/sifive_e.c | 25 -
> >  hw/riscv/sifive_u.c | 25 -
> >  hw/riscv/spike.c| 20 
> >  hw/riscv/virt.c | 25 -
> >  include/hw/riscv/sifive_e.h |  9 -
> >  include/hw/riscv/sifive_u.h |  9 -
> >  include/hw/riscv/virt.h |  9 -
> >  7 files changed, 122 deletions(-)
> >
> > diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
> > index 09c9d49..4872b68 100644
> > --- a/hw/riscv/sifive_e.c
> > +++ b/hw/riscv/sifive_e.c
> > @@ -194,24 +194,6 @@ static void riscv_sifive_e_init(MachineState
> *machine)
> >  }
> >  }
> >
> > -static int riscv_sifive_e_sysbus_device_init(SysBusDevice *sysbusdev)
> > -{
> > -return 0;
> > -}
> > -
> > -static void riscv_sifive_e_class_init(ObjectClass *klass, void *data)
> > -{
> > -SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
> > -k->init = riscv_sifive_e_sysbus_device_init;
> > -}
> > -
> > -static const TypeInfo riscv_sifive_e_device = {
> > -.name  = TYPE_SIFIVE_E,
> > -.parent= TYPE_SYS_BUS_DEVICE,
> > -.instance_size = sizeof(SiFiveEState),
> > -.class_init= riscv_sifive_e_class_init,
> > -};
> > -
> >  static void riscv_sifive_e_machine_init(MachineClass *mc)
> >  {
> >  mc->desc = "RISC-V Board compatible with SiFive E SDK";
> > @@ -220,10 +202,3 @@ static void riscv_sifive_e_machine_init(MachineClass
> *mc)
> >  }
> >
> >  DEFINE_MACHINE("sifive_e", riscv_sifive_e_machine_init)
> > -
> > -static void riscv_sifive_e_register_types(void)
> > -{
> > -type_register_static(_sifive_e_device);
> > -}
> > -
> > -type_init(riscv_sifive_e_register_types);
> > diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> > index 25df16c..083043a 100644
> > --- a/hw/riscv/sifive_u.c
> > +++ b/hw/riscv/sifive_u.c
> > @@ -302,31 +302,6 @@ static void riscv_sifive_u_init(MachineState
> *machine)
> >  SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
> >  }
> >
> > -static int riscv_sifive_u_sysbus_device_init(SysBusDevice *sysbusdev)
> > -{
> > -return 0;
> > -}
> > -
> > -static void riscv_sifive_u_class_init(ObjectClass *klass, void *data)
> > -{
> > -SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
> > -k->init = riscv_sifive_u_sysbus_device_init;
> > -}
> > -
> > -static const TypeInfo riscv_sifive_u_device = {
> > -.name  = TYPE_SIFIVE_U,
> > -.parent= TYPE_SYS_BUS_DEVICE,
> > -.instance_size = sizeof(SiFiveUState),
> > -.class_init= riscv_sifive_u_class_init,
> > -};
> > -
> > -static void riscv_sifive_u_register_types(void)
> > -{
> > -type_register_static(_sifive_u_device);
> > -}
> > -
> > -type_init(riscv_sifive_u_register_types);
> > -
> >  static void riscv_sifive_u_machine_init(MachineClass *mc)
> >  {
> >  mc->desc = "RISC-V Board compatible with SiFive U SDK";
> > diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
> > index 74edf33..64e585e 100644
> > --- a/hw/riscv/spike.c
> > +++ b/hw/riscv/spike.c
> > @@ -336,18 +336,6 @@ static void spike_v1_09_1_board_init(MachineState
> *machine)
> >  smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE,
> SIFIVE_TIME_BASE);
> >  }
> >
> > -static const TypeInfo spike_v_1_09_1_device = {
> > -.name  = TYPE_RISCV_SPIKE_V1_09_1_BOARD,
> > -.parent= TYPE_SYS_BUS_DEVICE,
> > -.instance_size = sizeof(SpikeState),
> > -};
> > -
> > -static const TypeInfo spike_v_1_10_0_device = {
> > -.name  = TYPE_RISCV_SPIKE_V1_10_0_BOARD,
> > -.parent= TYPE_SYS_BUS_DEVICE,
> > -.instance_size = sizeof(SpikeState),
> > -};
> > -
> >  static void spike_v1_09_1_machine_init(MachineClass *mc)
> >  {
> >  mc->desc = "RISC-V Spike Board (Privileged ISA v1.9.1)";
> > @@ -365,11 +353,3 @@ static void spike_v1_10_0_machine_init(MachineClass
> *mc)
> >
> >  DEFINE_MACHINE("spike_v1.9.1", spike_v1_09_1_machine_init)
> >  DEFINE_MACHINE("spike_v1.10", spike_v1_10_0_machine_init)
> > -
> > -static void riscv_spike_board_register_types(void)
> > -{
> > -type_register_static(_v_1_09_1_device);
> > -type_register_static(_v_1_10_0_device);
> > -}
> > -
> > -type_init(riscv_spike_board_register_types);
> > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> > index f1e3641..5913100 100644
> > --- a/hw/riscv/virt.c
> > +++

[Qemu-devel] [PATCH v1 07/22] RISC-V: Remove unused class definitions from

2018-03-06 Thread Michael Clark 
Removes a whole lot of unnecessary boilerplate code. Machines
don't need to be objects. The expansion of the SOC object model
for the RISC-V machines will happen in the future as SiFive
plans to add their FE310 and FU540 SOCs to QEMU. However, it
seems that this present boilerplate is complete unnecessary.

Signed-off-by: Michael Clark 
Signed-off-by: Palmer Dabbelt 
---
 hw/riscv/sifive_e.c | 25 -
 hw/riscv/sifive_u.c | 25 -
 hw/riscv/spike.c| 20 
 hw/riscv/virt.c | 25 -
 include/hw/riscv/sifive_e.h |  9 -
 include/hw/riscv/sifive_u.h |  9 -
 include/hw/riscv/virt.h |  9 -
 7 files changed, 122 deletions(-)

diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 09c9d49..4872b68 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -194,24 +194,6 @@ static void riscv_sifive_e_init(MachineState *machine)
 }
 }
 
-static int riscv_sifive_e_sysbus_device_init(SysBusDevice *sysbusdev)
-{
-return 0;
-}
-
-static void riscv_sifive_e_class_init(ObjectClass *klass, void *data)
-{
-SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
-k->init = riscv_sifive_e_sysbus_device_init;
-}
-
-static const TypeInfo riscv_sifive_e_device = {
-.name  = TYPE_SIFIVE_E,
-.parent= TYPE_SYS_BUS_DEVICE,
-.instance_size = sizeof(SiFiveEState),
-.class_init= riscv_sifive_e_class_init,
-};
-
 static void riscv_sifive_e_machine_init(MachineClass *mc)
 {
 mc->desc = "RISC-V Board compatible with SiFive E SDK";
@@ -220,10 +202,3 @@ static void riscv_sifive_e_machine_init(MachineClass *mc)
 }
 
 DEFINE_MACHINE("sifive_e", riscv_sifive_e_machine_init)
-
-static void riscv_sifive_e_register_types(void)
-{
-type_register_static(_sifive_e_device);
-}
-
-type_init(riscv_sifive_e_register_types);
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 25df16c..083043a 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -302,31 +302,6 @@ static void riscv_sifive_u_init(MachineState *machine)
 SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
 }
 
-static int riscv_sifive_u_sysbus_device_init(SysBusDevice *sysbusdev)
-{
-return 0;
-}
-
-static void riscv_sifive_u_class_init(ObjectClass *klass, void *data)
-{
-SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
-k->init = riscv_sifive_u_sysbus_device_init;
-}
-
-static const TypeInfo riscv_sifive_u_device = {
-.name  = TYPE_SIFIVE_U,
-.parent= TYPE_SYS_BUS_DEVICE,
-.instance_size = sizeof(SiFiveUState),
-.class_init= riscv_sifive_u_class_init,
-};
-
-static void riscv_sifive_u_register_types(void)
-{
-type_register_static(_sifive_u_device);
-}
-
-type_init(riscv_sifive_u_register_types);
-
 static void riscv_sifive_u_machine_init(MachineClass *mc)
 {
 mc->desc = "RISC-V Board compatible with SiFive U SDK";
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index 74edf33..64e585e 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -336,18 +336,6 @@ static void spike_v1_09_1_board_init(MachineState *machine)
 smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
 }
 
-static const TypeInfo spike_v_1_09_1_device = {
-.name  = TYPE_RISCV_SPIKE_V1_09_1_BOARD,
-.parent= TYPE_SYS_BUS_DEVICE,
-.instance_size = sizeof(SpikeState),
-};
-
-static const TypeInfo spike_v_1_10_0_device = {
-.name  = TYPE_RISCV_SPIKE_V1_10_0_BOARD,
-.parent= TYPE_SYS_BUS_DEVICE,
-.instance_size = sizeof(SpikeState),
-};
-
 static void spike_v1_09_1_machine_init(MachineClass *mc)
 {
 mc->desc = "RISC-V Spike Board (Privileged ISA v1.9.1)";
@@ -365,11 +353,3 @@ static void spike_v1_10_0_machine_init(MachineClass *mc)
 
 DEFINE_MACHINE("spike_v1.9.1", spike_v1_09_1_machine_init)
 DEFINE_MACHINE("spike_v1.10", spike_v1_10_0_machine_init)
-
-static void riscv_spike_board_register_types(void)
-{
-type_register_static(_v_1_09_1_device);
-type_register_static(_v_1_10_0_device);
-}
-
-type_init(riscv_spike_board_register_types);
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index f1e3641..5913100 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -380,24 +380,6 @@ static void riscv_virt_board_init(MachineState *machine)
 serial_hds[0], DEVICE_LITTLE_ENDIAN);
 }
 
-static int riscv_virt_board_sysbus_device_init(SysBusDevice *sysbusdev)
-{
-return 0;
-}
-
-static void riscv_virt_board_class_init(ObjectClass *klass, void *data)
-{
-SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
-k->init = riscv_virt_board_sysbus_device_init;
-}
-
-static const TypeInfo riscv_virt_board_device = {
-.name  = TYPE_RISCV_VIRT_BOARD,
-.parent= TYPE_SYS_BUS_DEVICE,
-.instance_size = sizeof(RISCVVirtState),
-.class_init= riscv_virt_board_class_init,
-};
-