[Qemu-devel] [PATCH v3 2/7] MIPS: Initial support of vt82686b south bridge used by fulong mini pc

2010-06-04 Thread Huacai Chen 
Signed-off-by: Huacai Chen zltjiang...@gmail.com
---
 Makefile.target |2 +-
 hw/pci_ids.h|8 +
 hw/vt82c686.c   |  579 +++
 hw/vt82c686.h   |   11 +
 4 files changed, 599 insertions(+), 1 deletions(-)
 create mode 100644 hw/vt82c686.c
 create mode 100644 hw/vt82c686.h

diff --git a/Makefile.target b/Makefile.target
index ac36e2c..92ba282 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -221,7 +221,7 @@ obj-mips-y += vga.o i8259.o
 obj-mips-y += g364fb.o jazz_led.o
 obj-mips-y += gt64xxx.o mc146818rtc.o
 obj-mips-y += piix4.o cirrus_vga.o
-obj-mips-$(CONFIG_FULONG) += bonito.o
+obj-mips-$(CONFIG_FULONG) += bonito.o vt82c686.o
 
 obj-microblaze-y = petalogix_s3adsp1800_mmu.o
 
diff --git a/hw/pci_ids.h b/hw/pci_ids.h
index fe7a121..39e9f1d 100644
--- a/hw/pci_ids.h
+++ b/hw/pci_ids.h
@@ -78,6 +78,14 @@
 
 #define PCI_VENDOR_ID_XILINX 0x10ee
 
+#define PCI_VENDOR_ID_VIA0x1106
+#define PCI_DEVICE_ID_VIA_ISA_BRIDGE 0x0686
+#define PCI_DEVICE_ID_VIA_IDE0x0571
+#define PCI_DEVICE_ID_VIA_UHCI   0x3038
+#define PCI_DEVICE_ID_VIA_ACPI   0x3057
+#define PCI_DEVICE_ID_VIA_AC97   0x3058
+#define PCI_DEVICE_ID_VIA_MC97   0x3068
+
 #define PCI_VENDOR_ID_MARVELL0x11ab
 
 #define PCI_VENDOR_ID_ENSONIQ0x1274
diff --git a/hw/vt82c686.c b/hw/vt82c686.c
new file mode 100644
index 000..d7d9eaf
--- /dev/null
+++ b/hw/vt82c686.c
@@ -0,0 +1,579 @@
+/*
+ * VT82C686B south bridge support
+ *
+ * Copyright (c) 2008 yajin (ya...@vm-kernel.org)
+ * Copyright (c) 2009 chenming (chenm...@rdc.faw.com.cn)
+ * Copyright (c) 2010 Huacai Chen (zltjiang...@gmail.com)
+ * This code is licensed under the GNU GPL v2.
+ */
+
+#include hw.h
+#include pc.h
+#include vt82c686.h
+#include i2c.h
+#include smbus.h
+#include pci.h
+#include isa.h
+#include sysbus.h
+#include mips.h
+#include apm.h
+#include acpi.h
+#include pm_smbus.h
+
+typedef uint32_t pci_addr_t;
+#include pci_host.h
+//#define DEBUG_VT82C686B
+
+#ifdef DEBUG_VT82C686B
+#define DPRINTF(fmt, ...) fprintf(stderr, %s:  fmt, __FUNCTION__, 
##__VA_ARGS__)
+#else
+#define DPRINTF(fmt, ...)
+#endif
+
+typedef struct SuperIOConfig
+{
+uint8_t config[0xff];
+uint8_t index;
+uint8_t data;
+} SuperIOConfig;
+
+typedef struct VT82C686BState {
+PCIDevice dev;
+SuperIOConfig *superio_conf;
+} VT82C686BState;
+
+static void superio_ioport_writeb(void *opaque, uint32_t addr, uint32_t data)
+{
+int can_write;
+SuperIOConfig *superio_conf = (SuperIOConfig *)opaque;
+
+DPRINTF(superio_ioport_writeb  address 0x%x  val 0x%x  \n, addr, data);
+if (addr == 0x3f0) {
+superio_conf-index = data  0xff;
+} else {
+/* 0x3f1 */
+switch (superio_conf-index) {
+case 0x00 ... 0xdf:
+case 0xe4:
+case 0xe5:
+case 0xe9 ... 0xed:
+case 0xf3:
+case 0xf5:
+case 0xf7:
+case 0xf9 ... 0xfb:
+case 0xfd ... 0xff:
+can_write = 0;
+break;
+default:
+can_write = 1;
+
+if (can_write) {
+switch (superio_conf-index) {
+case 0xe7:
+if ((data  0xff) != 0xfe) {
+DPRINTF(chage uart 1 base. unsupported yet \n);
+}
+break;
+case 0xe8:
+if ((data  0xff) != 0xbe) {
+DPRINTF(chage uart 2 base. unsupported yet \n);
+}
+break;
+
+default:
+superio_conf-config[superio_conf-index] = data  0xff;
+}
+}
+}
+superio_conf-config[superio_conf-index] = data  0xff;
+}
+}
+
+static uint32_t superio_ioport_readb(void *opaque, uint32_t addr)
+{
+SuperIOConfig *superio_conf = (SuperIOConfig *)opaque;
+
+DPRINTF(superio_ioport_readb  address 0x%x   \n, addr);
+return (superio_conf-config[superio_conf-index]);
+}
+
+static void vt82c686b_reset(void * opaque)
+{
+PCIDevice *d = opaque;
+uint8_t *pci_conf = d-config;
+VT82C686BState *vt82c = DO_UPCAST(VT82C686BState, dev, d);
+
+pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x00c0);
+pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
+ PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL);
+pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM);
+
+pci_conf[0x48] = 0x01; /* Miscellaneous Control 3 */
+pci_conf[0x4a] = 0x04; /* IDE interrupt Routing */
+pci_conf[0x4f] = 0x03; /* DMA/Master Mem Access Control 3 */
+pci_conf[0x50] = 0x2d; /* PnP DMA Request Control */
+pci_conf[0x59] = 0x04;
+pci_conf[0x5a] = 0x04; /* KBC/RTC Control*/
+pci_conf[0x5f] = 0x04;
+pci_conf[0x77] = 0x10; /* GPIO Control 1/2/3/4 */
+
+vt82c-superio_conf-config[0xe0] = 0x3c;
+

Re: [Qemu-devel] [PATCH v3 2/7] MIPS: Initial support of vt82686b south bridge used by fulong mini pc

2010-06-04 Thread Isaku Yamahata 
On Fri, Jun 04, 2010 at 04:38:30PM +0800, Huacai Chen wrote:
 Signed-off-by: Huacai Chen zltjiang...@gmail.com
 ---
  Makefile.target |2 +-
  hw/pci_ids.h|8 +
  hw/vt82c686.c   |  579 
 +++
  hw/vt82c686.h   |   11 +
  4 files changed, 599 insertions(+), 1 deletions(-)
  create mode 100644 hw/vt82c686.c
  create mode 100644 hw/vt82c686.h
 
 diff --git a/Makefile.target b/Makefile.target
 index ac36e2c..92ba282 100644
 --- a/Makefile.target
 +++ b/Makefile.target
 @@ -221,7 +221,7 @@ obj-mips-y += vga.o i8259.o
  obj-mips-y += g364fb.o jazz_led.o
  obj-mips-y += gt64xxx.o mc146818rtc.o
  obj-mips-y += piix4.o cirrus_vga.o
 -obj-mips-$(CONFIG_FULONG) += bonito.o
 +obj-mips-$(CONFIG_FULONG) += bonito.o vt82c686.o
  
  obj-microblaze-y = petalogix_s3adsp1800_mmu.o
  
 diff --git a/hw/pci_ids.h b/hw/pci_ids.h
 index fe7a121..39e9f1d 100644
 --- a/hw/pci_ids.h
 +++ b/hw/pci_ids.h
 @@ -78,6 +78,14 @@
  
  #define PCI_VENDOR_ID_XILINX 0x10ee
  
 +#define PCI_VENDOR_ID_VIA0x1106
 +#define PCI_DEVICE_ID_VIA_ISA_BRIDGE 0x0686
 +#define PCI_DEVICE_ID_VIA_IDE0x0571
 +#define PCI_DEVICE_ID_VIA_UHCI   0x3038
 +#define PCI_DEVICE_ID_VIA_ACPI   0x3057
 +#define PCI_DEVICE_ID_VIA_AC97   0x3058
 +#define PCI_DEVICE_ID_VIA_MC97   0x3068
 +
  #define PCI_VENDOR_ID_MARVELL0x11ab
  
  #define PCI_VENDOR_ID_ENSONIQ0x1274
 diff --git a/hw/vt82c686.c b/hw/vt82c686.c
 new file mode 100644
 index 000..d7d9eaf
 --- /dev/null
 +++ b/hw/vt82c686.c
 @@ -0,0 +1,579 @@
 +/*
 + * VT82C686B south bridge support
 + *
 + * Copyright (c) 2008 yajin (ya...@vm-kernel.org)
 + * Copyright (c) 2009 chenming (chenm...@rdc.faw.com.cn)
 + * Copyright (c) 2010 Huacai Chen (zltjiang...@gmail.com)
 + * This code is licensed under the GNU GPL v2.
 + */
 +
 +#include hw.h
 +#include pc.h
 +#include vt82c686.h
 +#include i2c.h
 +#include smbus.h
 +#include pci.h
 +#include isa.h
 +#include sysbus.h
 +#include mips.h
 +#include apm.h
 +#include acpi.h
 +#include pm_smbus.h
 +
 +typedef uint32_t pci_addr_t;
 +#include pci_host.h
 +//#define DEBUG_VT82C686B
 +
 +#ifdef DEBUG_VT82C686B
 +#define DPRINTF(fmt, ...) fprintf(stderr, %s:  fmt, __FUNCTION__, 
 ##__VA_ARGS__)
 +#else
 +#define DPRINTF(fmt, ...)
 +#endif
 +
 +typedef struct SuperIOConfig
 +{
 +uint8_t config[0xff];
 +uint8_t index;
 +uint8_t data;
 +} SuperIOConfig;
 +
 +typedef struct VT82C686BState {
 +PCIDevice dev;
 +SuperIOConfig *superio_conf;
 +} VT82C686BState;
 +
 +static void superio_ioport_writeb(void *opaque, uint32_t addr, uint32_t data)
 +{
 +int can_write;
 +SuperIOConfig *superio_conf = (SuperIOConfig *)opaque;
 +
 +DPRINTF(superio_ioport_writeb  address 0x%x  val 0x%x  \n, addr, data);
 +if (addr == 0x3f0) {
 +superio_conf-index = data  0xff;
 +} else {
 +/* 0x3f1 */
 +switch (superio_conf-index) {
 +case 0x00 ... 0xdf:
 +case 0xe4:
 +case 0xe5:
 +case 0xe9 ... 0xed:
 +case 0xf3:
 +case 0xf5:
 +case 0xf7:
 +case 0xf9 ... 0xfb:
 +case 0xfd ... 0xff:
 +can_write = 0;
 +break;
 +default:
 +can_write = 1;
 +
 +if (can_write) {
 +switch (superio_conf-index) {
 +case 0xe7:
 +if ((data  0xff) != 0xfe) {
 +DPRINTF(chage uart 1 base. unsupported yet \n);
 +}
 +break;
 +case 0xe8:
 +if ((data  0xff) != 0xbe) {
 +DPRINTF(chage uart 2 base. unsupported yet \n);
 +}
 +break;
 +
 +default:
 +superio_conf-config[superio_conf-index] = data  0xff;
 +}
 +}
 +}
 +superio_conf-config[superio_conf-index] = data  0xff;
 +}
 +}
 +
 +static uint32_t superio_ioport_readb(void *opaque, uint32_t addr)
 +{
 +SuperIOConfig *superio_conf = (SuperIOConfig *)opaque;
 +
 +DPRINTF(superio_ioport_readb  address 0x%x   \n, addr);
 +return (superio_conf-config[superio_conf-index]);
 +}
 +
 +static void vt82c686b_reset(void * opaque)
 +{
 +PCIDevice *d = opaque;
 +uint8_t *pci_conf = d-config;
 +VT82C686BState *vt82c = DO_UPCAST(VT82C686BState, dev, d);
 +
 +pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x00c0);
 +pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY 
 |
 + PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL);
 +pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM);
 +
 +pci_conf[0x48] = 0x01; /* Miscellaneous Control 3 */
 +pci_conf[0x4a] = 0x04; /* IDE interrupt Routing */
 +pci_conf[0x4f] = 0x03; /* DMA/Master Mem Access Control 3 */
 +pci_conf[0x50] = 0x2d; /* PnP DMA