Re: [Qemu-devel] [PATCH v5 09/23] RISC-V TCG Code Generation

[Emilio G. Cota]

On Wed, Feb 14, 2018 at 13:13:09 -0800, Richard Henderson wrote:
> On 02/14/2018 11:52 AM, Emilio G. Cota wrote:
> > Should I send those patches to the list, or let Michael squash their 
> > changes?
> 
> That's up to you, I guess.  I don't mind if it goes in before or after merge.

OK, will send to the list once the merge is complete.

Thanks,

Emilio

Re: [Qemu-devel] [PATCH v5 09/23] RISC-V TCG Code Generation

[Richard Henderson]

On 02/14/2018 11:52 AM, Emilio G. Cota wrote:
> Should I send those patches to the list, or let Michael squash their changes?

That's up to you, I guess.  I don't mind if it goes in before or after merge.


r~

Re: [Qemu-devel] [PATCH v5 09/23] RISC-V TCG Code Generation

[Emilio G. Cota]

On Wed, Feb 14, 2018 at 11:14:48 -0800, Richard Henderson wrote:
> On 02/13/2018 04:10 PM, Emilio G. Cota wrote:
> > On Tue, Feb 13, 2018 at 14:10:20 -0800, Richard Henderson wrote:
> >> On 02/13/2018 01:55 PM, Emilio G. Cota wrote:
> >>> Are we planning to use BS_STOP in the future? I see it has no setters,
> >>> although we check for it in gen_intermediate_code:
> >>
> >> No, but the whole port should be converted to exec/translator.h, which 
> >> defines
> >> DisasJumpType.  Not something I'm going to require on initial submission 
> >> until
> >> we've gotten most of the other targets cleaned up.
> > 
> > I see. I've just done the conversion for v5:
> >   https://github.com/cota/qemu/commits/riscv-v5-trloop
> > 
> > Can you please take a look?
> 
> Looks ok.  Watch your formatting, e.g { } on the same line.

Thanks, checkpatch didn't complain about that one though.

Should I send those patches to the list, or let Michael squash their changes?

E.

Re: [Qemu-devel] [PATCH v5 09/23] RISC-V TCG Code Generation

[Richard Henderson]

On 02/13/2018 04:10 PM, Emilio G. Cota wrote:
> On Tue, Feb 13, 2018 at 14:10:20 -0800, Richard Henderson wrote:
>> On 02/13/2018 01:55 PM, Emilio G. Cota wrote:
>>> Are we planning to use BS_STOP in the future? I see it has no setters,
>>> although we check for it in gen_intermediate_code:
>>
>> No, but the whole port should be converted to exec/translator.h, which 
>> defines
>> DisasJumpType.  Not something I'm going to require on initial submission 
>> until
>> we've gotten most of the other targets cleaned up.
> 
> I see. I've just done the conversion for v5:
>   https://github.com/cota/qemu/commits/riscv-v5-trloop
> 
> Can you please take a look?

Looks ok.  Watch your formatting, e.g { } on the same line.


r~

Re: [Qemu-devel] [PATCH v5 09/23] RISC-V TCG Code Generation

[Emilio G. Cota]

On Tue, Feb 13, 2018 at 14:10:20 -0800, Richard Henderson wrote:
> On 02/13/2018 01:55 PM, Emilio G. Cota wrote:
> > Are we planning to use BS_STOP in the future? I see it has no setters,
> > although we check for it in gen_intermediate_code:
> 
> No, but the whole port should be converted to exec/translator.h, which defines
> DisasJumpType.  Not something I'm going to require on initial submission until
> we've gotten most of the other targets cleaned up.

I see. I've just done the conversion for v5:
  https://github.com/cota/qemu/commits/riscv-v5-trloop

Can you please take a look?

Thanks,

Emilio

Re: [Qemu-devel] [PATCH v5 09/23] RISC-V TCG Code Generation

[Richard Henderson]

On 02/13/2018 01:55 PM, Emilio G. Cota wrote:
> On Thu, Feb 08, 2018 at 14:28:34 +1300, Michael Clark wrote:
>> TCG code generation for the RV32IMAFDC and RV64IMAFDC. The QEMU
>> RISC-V code generator has complete coverage for the Base ISA v2.2,
>> Privileged ISA v1.9.1 and Privileged ISA v1.10:
>>
>> - RISC-V Instruction Set Manual Volume I: User-Level ISA Version 2.2
>> - RISC-V Instruction Set Manual Volume II: Privileged ISA Version 1.9.1
>> - RISC-V Instruction Set Manual Volume II: Privileged ISA Version 1.10
>>
>> Reviewed-by: Richard Henderson 
>> Signed-off-by: Michael Clark 
>> ---
> (snip)
>> +++ b/target/riscv/translate.c
> (snip)
>> +enum {
>> +BS_NONE = 0, /* When seen outside of translation while loop, 
>> indicates
>> + need to exit tb due to end of page. */
>> +BS_STOP = 1, /* Need to exit tb for syscall, sret, etc. */
> 
> Are we planning to use BS_STOP in the future? I see it has no setters,
> although we check for it in gen_intermediate_code:

No, but the whole port should be converted to exec/translator.h, which defines
DisasJumpType.  Not something I'm going to require on initial submission until
we've gotten most of the other targets cleaned up.


r~

Re: [Qemu-devel] [PATCH v5 09/23] RISC-V TCG Code Generation

[Emilio G. Cota]

On Thu, Feb 08, 2018 at 14:28:34 +1300, Michael Clark wrote:
> TCG code generation for the RV32IMAFDC and RV64IMAFDC. The QEMU
> RISC-V code generator has complete coverage for the Base ISA v2.2,
> Privileged ISA v1.9.1 and Privileged ISA v1.10:
> 
> - RISC-V Instruction Set Manual Volume I: User-Level ISA Version 2.2
> - RISC-V Instruction Set Manual Volume II: Privileged ISA Version 1.9.1
> - RISC-V Instruction Set Manual Volume II: Privileged ISA Version 1.10
> 
> Reviewed-by: Richard Henderson 
> Signed-off-by: Michael Clark 
> ---
(snip)
> +++ b/target/riscv/translate.c
(snip)
> +/* Address comparion failure.  However, we still need to
> +   provide the memory barrier implied by AQ/RL.  */

s/comparion/comparison/

E.

Re: [Qemu-devel] [PATCH v5 09/23] RISC-V TCG Code Generation

[Emilio G. Cota]

On Thu, Feb 08, 2018 at 14:28:34 +1300, Michael Clark wrote:
> TCG code generation for the RV32IMAFDC and RV64IMAFDC. The QEMU
> RISC-V code generator has complete coverage for the Base ISA v2.2,
> Privileged ISA v1.9.1 and Privileged ISA v1.10:
> 
> - RISC-V Instruction Set Manual Volume I: User-Level ISA Version 2.2
> - RISC-V Instruction Set Manual Volume II: Privileged ISA Version 1.9.1
> - RISC-V Instruction Set Manual Volume II: Privileged ISA Version 1.10
> 
> Reviewed-by: Richard Henderson 
> Signed-off-by: Michael Clark 
> ---
(snip)
> +++ b/target/riscv/translate.c
(snip)
> +enum {
> +BS_NONE = 0, /* When seen outside of translation while loop, 
> indicates
> + need to exit tb due to end of page. */
> +BS_STOP = 1, /* Need to exit tb for syscall, sret, etc. */

Are we planning to use BS_STOP in the future? I see it has no setters,
although we check for it in gen_intermediate_code:

(snip)
> +switch (ctx.bstate) {
> +case BS_STOP:
> +gen_goto_tb(, 0, ctx.pc);
> +break;
> +case BS_NONE: /* handle end of page - DO NOT CHAIN. See gen_goto_tb. */

Should we get rid of it?

Emilio

[Qemu-devel] [PATCH v5 09/23] RISC-V TCG Code Generation

[Michael Clark]

TCG code generation for the RV32IMAFDC and RV64IMAFDC. The QEMU
RISC-V code generator has complete coverage for the Base ISA v2.2,
Privileged ISA v1.9.1 and Privileged ISA v1.10:

- RISC-V Instruction Set Manual Volume I: User-Level ISA Version 2.2
- RISC-V Instruction Set Manual Volume II: Privileged ISA Version 1.9.1
- RISC-V Instruction Set Manual Volume II: Privileged ISA Version 1.10

Reviewed-by: Richard Henderson 
Signed-off-by: Michael Clark 
---
 target/riscv/instmap.h   |  366 +
 target/riscv/translate.c | 1970 ++
 2 files changed, 2336 insertions(+)
 create mode 100644 target/riscv/instmap.h
 create mode 100644 target/riscv/translate.c

diff --git a/target/riscv/instmap.h b/target/riscv/instmap.h
new file mode 100644
index 000..00baba8
--- /dev/null
+++ b/target/riscv/instmap.h
@@ -0,0 +1,366 @@
+/*
+ * RISC-V emulation for qemu: Instruction decode helpers
+ *
+ * Author: Sagar Karandikar, sag...@eecs.berkeley.edu
+ *
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see .
+ */
+
+#define MASK_OP_MAJOR(op)  (op & 0x7F)
+enum {
+/* rv32i, rv64i, rv32m */
+OPC_RISC_LUI= (0x37),
+OPC_RISC_AUIPC  = (0x17),
+OPC_RISC_JAL= (0x6F),
+OPC_RISC_JALR   = (0x67),
+OPC_RISC_BRANCH = (0x63),
+OPC_RISC_LOAD   = (0x03),
+OPC_RISC_STORE  = (0x23),
+OPC_RISC_ARITH_IMM  = (0x13),
+OPC_RISC_ARITH  = (0x33),
+OPC_RISC_FENCE  = (0x0F),
+OPC_RISC_SYSTEM = (0x73),
+
+/* rv64i, rv64m */
+OPC_RISC_ARITH_IMM_W = (0x1B),
+OPC_RISC_ARITH_W = (0x3B),
+
+/* rv32a, rv64a */
+OPC_RISC_ATOMIC = (0x2F),
+
+/* floating point */
+OPC_RISC_FP_LOAD = (0x7),
+OPC_RISC_FP_STORE = (0x27),
+
+OPC_RISC_FMADD = (0x43),
+OPC_RISC_FMSUB = (0x47),
+OPC_RISC_FNMSUB = (0x4B),
+OPC_RISC_FNMADD = (0x4F),
+
+OPC_RISC_FP_ARITH = (0x53),
+};
+
+#define MASK_OP_ARITH(op)   (MASK_OP_MAJOR(op) | (op & ((0x7 << 12) | \
+(0x7F << 25
+enum {
+OPC_RISC_ADD   = OPC_RISC_ARITH | (0x0 << 12) | (0x00 << 25),
+OPC_RISC_SUB   = OPC_RISC_ARITH | (0x0 << 12) | (0x20 << 25),
+OPC_RISC_SLL   = OPC_RISC_ARITH | (0x1 << 12) | (0x00 << 25),
+OPC_RISC_SLT   = OPC_RISC_ARITH | (0x2 << 12) | (0x00 << 25),
+OPC_RISC_SLTU  = OPC_RISC_ARITH | (0x3 << 12) | (0x00 << 25),
+OPC_RISC_XOR   = OPC_RISC_ARITH | (0x4 << 12) | (0x00 << 25),
+OPC_RISC_SRL   = OPC_RISC_ARITH | (0x5 << 12) | (0x00 << 25),
+OPC_RISC_SRA   = OPC_RISC_ARITH | (0x5 << 12) | (0x20 << 25),
+OPC_RISC_OR= OPC_RISC_ARITH | (0x6 << 12) | (0x00 << 25),
+OPC_RISC_AND   = OPC_RISC_ARITH | (0x7 << 12) | (0x00 << 25),
+
+/* RV64M */
+OPC_RISC_MUL= OPC_RISC_ARITH | (0x0 << 12) | (0x01 << 25),
+OPC_RISC_MULH   = OPC_RISC_ARITH | (0x1 << 12) | (0x01 << 25),
+OPC_RISC_MULHSU = OPC_RISC_ARITH | (0x2 << 12) | (0x01 << 25),
+OPC_RISC_MULHU  = OPC_RISC_ARITH | (0x3 << 12) | (0x01 << 25),
+
+OPC_RISC_DIV= OPC_RISC_ARITH | (0x4 << 12) | (0x01 << 25),
+OPC_RISC_DIVU   = OPC_RISC_ARITH | (0x5 << 12) | (0x01 << 25),
+OPC_RISC_REM= OPC_RISC_ARITH | (0x6 << 12) | (0x01 << 25),
+OPC_RISC_REMU   = OPC_RISC_ARITH | (0x7 << 12) | (0x01 << 25),
+};
+
+
+#define MASK_OP_ARITH_IMM(op)   (MASK_OP_MAJOR(op) | (op & (0x7 << 12)))
+enum {
+OPC_RISC_ADDI   = OPC_RISC_ARITH_IMM | (0x0 << 12),
+OPC_RISC_SLTI   = OPC_RISC_ARITH_IMM | (0x2 << 12),
+OPC_RISC_SLTIU  = OPC_RISC_ARITH_IMM | (0x3 << 12),
+OPC_RISC_XORI   = OPC_RISC_ARITH_IMM | (0x4 << 12),
+OPC_RISC_ORI= OPC_RISC_ARITH_IMM | (0x6 << 12),
+OPC_RISC_ANDI   = OPC_RISC_ARITH_IMM | (0x7 << 12),
+OPC_RISC_SLLI   = OPC_RISC_ARITH_IMM | (0x1 << 12), /* additional part of
+   IMM */
+OPC_RISC_SHIFT_RIGHT_I = OPC_RISC_ARITH_IMM | (0x5 << 12) /* SRAI, SRLI */
+};
+
+#define MASK_OP_BRANCH(op) (MASK_OP_MAJOR(op) | (op & (0x7 << 12)))
+enum {
+OPC_RISC_BEQ  = OPC_RISC_BRANCH  | (0x0  << 12),
+OPC_RISC_BNE  = OPC_RISC_BRANCH  | (0x1  << 12),
+OPC_RISC_BLT  = OPC_RISC_BRANCH  | (0x4  << 12),
+OPC_RISC_BGE  = OPC_RISC_BRANCH  | (0x5  << 12),
+OPC_RISC_BLTU = OPC_RISC_BRANCH  | (0x6  << 12),
+OPC_RISC_BGEU = OPC_RISC_BRANCH  |