On Wed, Feb 14, 2018 at 13:13:09 -0800, Richard Henderson wrote:
> On 02/14/2018 11:52 AM, Emilio G. Cota wrote:
> > Should I send those patches to the list, or let Michael squash their
> > changes?
>
> That's up to you, I guess. I don't mind if it goes in before or after merge.
OK, will send
On 02/14/2018 11:52 AM, Emilio G. Cota wrote:
> Should I send those patches to the list, or let Michael squash their changes?
That's up to you, I guess. I don't mind if it goes in before or after merge.
r~
On Wed, Feb 14, 2018 at 11:14:48 -0800, Richard Henderson wrote:
> On 02/13/2018 04:10 PM, Emilio G. Cota wrote:
> > On Tue, Feb 13, 2018 at 14:10:20 -0800, Richard Henderson wrote:
> >> On 02/13/2018 01:55 PM, Emilio G. Cota wrote:
> >>> Are we planning to use BS_STOP in the future? I see it has
On 02/13/2018 04:10 PM, Emilio G. Cota wrote:
> On Tue, Feb 13, 2018 at 14:10:20 -0800, Richard Henderson wrote:
>> On 02/13/2018 01:55 PM, Emilio G. Cota wrote:
>>> Are we planning to use BS_STOP in the future? I see it has no setters,
>>> although we check for it in gen_intermediate_code:
>>
>>
On Tue, Feb 13, 2018 at 14:10:20 -0800, Richard Henderson wrote:
> On 02/13/2018 01:55 PM, Emilio G. Cota wrote:
> > Are we planning to use BS_STOP in the future? I see it has no setters,
> > although we check for it in gen_intermediate_code:
>
> No, but the whole port should be converted to
On 02/13/2018 01:55 PM, Emilio G. Cota wrote:
> On Thu, Feb 08, 2018 at 14:28:34 +1300, Michael Clark wrote:
>> TCG code generation for the RV32IMAFDC and RV64IMAFDC. The QEMU
>> RISC-V code generator has complete coverage for the Base ISA v2.2,
>> Privileged ISA v1.9.1 and Privileged ISA v1.10:
On Thu, Feb 08, 2018 at 14:28:34 +1300, Michael Clark wrote:
> TCG code generation for the RV32IMAFDC and RV64IMAFDC. The QEMU
> RISC-V code generator has complete coverage for the Base ISA v2.2,
> Privileged ISA v1.9.1 and Privileged ISA v1.10:
>
> - RISC-V Instruction Set Manual Volume I:
On Thu, Feb 08, 2018 at 14:28:34 +1300, Michael Clark wrote:
> TCG code generation for the RV32IMAFDC and RV64IMAFDC. The QEMU
> RISC-V code generator has complete coverage for the Base ISA v2.2,
> Privileged ISA v1.9.1 and Privileged ISA v1.10:
>
> - RISC-V Instruction Set Manual Volume I: