Qemu virt machine can support few cache events and cycle/instret counters. It also supports counter overflow for these events.
Add a DT node so that OpenSBI/Linux kernel is aware of the virt machine capabilities. Signed-off-by: Atish Patra <atish.pa...@wdc.com> --- hw/riscv/virt.c | 25 +++++++++++++++++++-- target/riscv/pmu.c | 55 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 78 insertions(+), 2 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 4a3cd2599a5e..197390fe5627 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -28,6 +28,7 @@ #include "hw/qdev-properties.h" #include "hw/char/serial.h" #include "target/riscv/cpu.h" +#include "target/riscv/pmu.h" #include "hw/riscv/riscv_hart.h" #include "hw/riscv/virt.h" #include "hw/riscv/boot.h" @@ -42,6 +43,7 @@ #include "hw/pci/pci.h" #include "hw/pci-host/gpex.h" #include "hw/display/ramfb.h" +#include <libfdt.h> static const MemMapEntry virt_memmap[] = { [VIRT_DEBUG] = { 0x0, 0x100 }, @@ -184,14 +186,14 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, int i, cpu, socket; MachineState *mc = MACHINE(s); uint64_t addr, size; - uint32_t *clint_cells, *plic_cells; + uint32_t *clint_cells, *plic_cells, *pmu_int_cells; unsigned long clint_addr, plic_addr; uint32_t plic_phandle[MAX_NODES]; uint32_t cpu_phandle, intc_phandle, test_phandle; uint32_t phandle = 1, plic_mmio_phandle = 1; uint32_t plic_pcie_phandle = 1, plic_virtio_phandle = 1; char *mem_name, *cpu_name, *core_name, *intc_name; - char *name, *clint_name, *plic_name, *clust_name; + char *name, *clint_name, *plic_name, *clust_name, *pmu_name; hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; hwaddr flashbase = virt_memmap[VIRT_FLASH].base; static const char * const clint_compat[2] = { @@ -240,6 +242,7 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); + pmu_int_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) { cpu_phandle = phandle++; @@ -282,6 +285,9 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT); + pmu_int_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandle); + pmu_int_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_PMU_OVF); + core_name = g_strdup_printf("%s/core%d", clust_name, cpu); qemu_fdt_add_subnode(fdt, core_name); qemu_fdt_setprop_cell(fdt, core_name, "cpu", cpu_phandle); @@ -291,6 +297,21 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, g_free(cpu_name); } + pmu_name = g_strdup_printf("/soc/pmu"); + qemu_fdt_add_subnode(fdt, pmu_name); + qemu_fdt_setprop_string(fdt, pmu_name, "compatible", "riscv,pmu"); + RISCVCPU cpu = s->soc[0].harts[0]; + if (cpu.cfg.ext_sscof) { + qemu_fdt_setprop_cell(fdt, pmu_name, "#interrupt-cells", 1); + qemu_fdt_setprop(fdt, pmu_name, "interrupts-extended", + pmu_int_cells, + s->soc[socket].num_harts * sizeof(uint32_t) * 2); + } + + riscv_pmu_generate_fdt_node(fdt, pmu_name); + g_free(pmu_int_cells); + g_free(pmu_name); + addr = memmap[VIRT_DRAM].base + riscv_socket_mem_offset(mc, socket); size = riscv_socket_mem_size(mc, socket); mem_name = g_strdup_printf("/memory@%lx", (long)addr); diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c index a4c0044ff822..a93b61daf00a 100644 --- a/target/riscv/pmu.c +++ b/target/riscv/pmu.c @@ -19,9 +19,64 @@ #include "qemu/osdep.h" #include "cpu.h" #include "pmu.h" +#include "sysemu/device_tree.h" #define RISCV_TIMEBASE_FREQ 1000000000 /* 1Ghz */ +/** + * To keep it simple, any event can be mapped to any programmable counters in + * QEMU. The generic cycle & instruction count events can also be monitored + * using programmable counters. In that case, mcycle & minstret must continue + * to provide the correct value as well. + */ +void riscv_pmu_generate_fdt_node(void *fdt, char *pmu_name) +{ + uint32_t fdt_event_map[6] = {}; + uint32_t fdt_event_ctr_map[20] = {}; + uint32_t fdt_raw_event_ctr_map[6] = {}; + + fdt_event_map[0] = cpu_to_be32(0x00000009); + fdt_event_map[1] = cpu_to_be32(0x00000000); + fdt_event_map[2] = cpu_to_be32(0x00000200); + fdt_event_map[3] = cpu_to_be32(0x00010000); + fdt_event_map[4] = cpu_to_be32(0x00000100); + fdt_event_map[5] = cpu_to_be32(0x00000002); + qemu_fdt_setprop(fdt, pmu_name, "pmu,event-to-mhpmevent", + fdt_event_map, sizeof(fdt_event_map)); + + fdt_event_ctr_map[0] = cpu_to_be32(0x00000001); + fdt_event_ctr_map[1] = cpu_to_be32(0x00000001); + fdt_event_ctr_map[2] = cpu_to_be32(0x00000FF9); + fdt_event_ctr_map[3] = cpu_to_be32(0x00000002); + fdt_event_ctr_map[4] = cpu_to_be32(0x00000002); + fdt_event_ctr_map[5] = cpu_to_be32(0x00000FFC); + + fdt_event_ctr_map[6] = cpu_to_be32(0x00010019); + fdt_event_ctr_map[7] = cpu_to_be32(0x00010019); + fdt_event_ctr_map[8] = cpu_to_be32(0x00001F0); + + fdt_event_ctr_map[9] = cpu_to_be32(0x0001001B); + fdt_event_ctr_map[10] = cpu_to_be32(0x0001001B); + fdt_event_ctr_map[11] = cpu_to_be32(0x00001F0); + + fdt_event_ctr_map[12] = cpu_to_be32(0x00010021); + fdt_event_ctr_map[13] = cpu_to_be32(0x00010021); + fdt_event_ctr_map[14] = cpu_to_be32(0x00001F0); + + qemu_fdt_setprop(fdt, pmu_name, "pmu,event-to-mhpmcounters", + fdt_event_ctr_map, sizeof(fdt_event_ctr_map)); + + fdt_raw_event_ctr_map[0] = cpu_to_be32(0x00000000); + fdt_raw_event_ctr_map[1] = cpu_to_be32(0x00020002); + fdt_raw_event_ctr_map[2] = cpu_to_be32(0x00000F00); + fdt_raw_event_ctr_map[3] = cpu_to_be32(0x00000000); + fdt_raw_event_ctr_map[4] = cpu_to_be32(0x00020003); + fdt_raw_event_ctr_map[5] = cpu_to_be32(0x000000F0); + qemu_fdt_setprop(fdt, pmu_name, "pmu,raw-event-to-mhpmcounters", + fdt_raw_event_ctr_map, + sizeof(fdt_raw_event_ctr_map)); +} + static bool riscv_pmu_counter_valid(RISCVCPU *cpu, uint32_t ctr_idx) { if (ctr_idx < 3 || ctr_idx >= RV_MAX_MHPMCOUNTERS || -- 2.31.1