Re: [PATCH] hw/cxl: Fix missing write mask for HDM decoder target list registers
On Mon, 6 Jun 2022 10:39:52 -0700 Ben Widawsky wrote: > On 22-05-31 13:39:53, Jonathan Cameron wrote: > > Without being able to write these registers, no interleaving is possible. > > More refined checks of HDM register state on commit to follow. > > > > Signed-off-by: Jonathan Cameron > > --- > > hw/cxl/cxl-component-utils.c | 2 ++ > > 1 file changed, 2 insertions(+) > > > > diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c > > index 7985c9bfca..993248b5c0 100644 > > --- a/hw/cxl/cxl-component-utils.c > > +++ b/hw/cxl/cxl-component-utils.c > > @@ -174,6 +174,8 @@ static void hdm_init_common(uint32_t *reg_state, > > uint32_t *write_msk) > > write_msk[R_CXL_HDM_DECODER0_SIZE_LO + i * 0x20] = 0xf000; > > write_msk[R_CXL_HDM_DECODER0_SIZE_HI + i * 0x20] = 0x; > > write_msk[R_CXL_HDM_DECODER0_CTRL + i * 0x20] = 0x13ff; > > +write_msk[R_CXL_HDM_DECODER0_TARGET_LIST_LO + i * 0x20] = > > 0x; > > +write_msk[R_CXL_HDM_DECODER0_TARGET_LIST_HI + i * 0x20] = > > 0x; > > I wonder if this should be 0. It will be weird for endpoints to have a skip > value of 0xff. For EP _LO should be 0xf000. But we haven't implemented skip yet IIRC. It should be all bits set for host bridges (or switches) and that's the bug this is fixing. We have access to the device type at the caller of this function, so I can make it right for both changes with a trivial change. Will send a v2 shortly... Thanks, Jonathan > > > } > > } > > > > -- > > 2.32.0 > >
Re: [PATCH] hw/cxl: Fix missing write mask for HDM decoder target list registers
On 22-05-31 13:39:53, Jonathan Cameron wrote: > Without being able to write these registers, no interleaving is possible. > More refined checks of HDM register state on commit to follow. > > Signed-off-by: Jonathan Cameron > --- > hw/cxl/cxl-component-utils.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c > index 7985c9bfca..993248b5c0 100644 > --- a/hw/cxl/cxl-component-utils.c > +++ b/hw/cxl/cxl-component-utils.c > @@ -174,6 +174,8 @@ static void hdm_init_common(uint32_t *reg_state, uint32_t > *write_msk) > write_msk[R_CXL_HDM_DECODER0_SIZE_LO + i * 0x20] = 0xf000; > write_msk[R_CXL_HDM_DECODER0_SIZE_HI + i * 0x20] = 0x; > write_msk[R_CXL_HDM_DECODER0_CTRL + i * 0x20] = 0x13ff; > +write_msk[R_CXL_HDM_DECODER0_TARGET_LIST_LO + i * 0x20] = 0x; > +write_msk[R_CXL_HDM_DECODER0_TARGET_LIST_HI + i * 0x20] = 0x; I wonder if this should be 0. It will be weird for endpoints to have a skip value of 0xff. > } > } > > -- > 2.32.0 >
[PATCH] hw/cxl: Fix missing write mask for HDM decoder target list registers
Without being able to write these registers, no interleaving is possible. More refined checks of HDM register state on commit to follow. Signed-off-by: Jonathan Cameron --- hw/cxl/cxl-component-utils.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c index 7985c9bfca..993248b5c0 100644 --- a/hw/cxl/cxl-component-utils.c +++ b/hw/cxl/cxl-component-utils.c @@ -174,6 +174,8 @@ static void hdm_init_common(uint32_t *reg_state, uint32_t *write_msk) write_msk[R_CXL_HDM_DECODER0_SIZE_LO + i * 0x20] = 0xf000; write_msk[R_CXL_HDM_DECODER0_SIZE_HI + i * 0x20] = 0x; write_msk[R_CXL_HDM_DECODER0_CTRL + i * 0x20] = 0x13ff; +write_msk[R_CXL_HDM_DECODER0_TARGET_LIST_LO + i * 0x20] = 0x; +write_msk[R_CXL_HDM_DECODER0_TARGET_LIST_HI + i * 0x20] = 0x; } } -- 2.32.0
