On Thu, 14 Nov 2019 at 20:45, Alexander Graf wrote:
> On 14.11.19 15:42, Peter Maydell wrote:
> > Is that OK?
>
> It's much better. Will you just fix it up inline for me please? :)
Sure :-)
-- PMM
On 14.11.19 15:42, Peter Maydell wrote:
On Tue, 12 Nov 2019 at 11:57, Peter Maydell wrote:
On Tue, 12 Nov 2019 at 07:28, Alexander Graf wrote:
I still think that being consistent with the actual PL031 spec is
preferable though. If any real world guest breaks because of this, we
can still
On Tue, 12 Nov 2019 at 11:57, Peter Maydell wrote:
> On Tue, 12 Nov 2019 at 07:28, Alexander Graf wrote:
> > I still think that being consistent with the actual PL031 spec is
> > preferable though. If any real world guest breaks because of this, we
> > can still revert this patch and document
On Tue, 12 Nov 2019 at 07:28, Alexander Graf wrote:
>
> Hey Peter,
>
> On 08.11.19 17:58, Peter Maydell wrote:
> > Did you find this because you had a guest that assumed the
> > other behaviour? This bug has been in QEMU for a very long time,
> > and it seems odd for a guest to deliberately
Hey Peter,
On 08.11.19 17:58, Peter Maydell wrote:
On Mon, 4 Nov 2019 at 11:52, Alexander Graf wrote:
The current pl031 RTCICR register implementation always clears the IRQ
pending status on a register write, regardless of the value it writes.
To justify that behavior, it references the
On Mon, 4 Nov 2019 at 11:52, Alexander Graf wrote:
>
> The current pl031 RTCICR register implementation always clears the IRQ
> pending status on a register write, regardless of the value it writes.
>
> To justify that behavior, it references the arm926e documentation
> (DDI0287B) and indicates
The current pl031 RTCICR register implementation always clears the IRQ
pending status on a register write, regardless of the value it writes.
To justify that behavior, it references the arm926e documentation
(DDI0287B) and indicates that said document states that any write clears
the internal IRQ
