On 4/26/22 05:42, Damien Hedde wrote:
@@ -1587,6 +1587,9 @@ static void arm_cpu_realizefn(DeviceState *dev, Error
**errp)
unset_feature(env, ARM_FEATURE_NEON);
t = cpu->isar.id_aa64isar0;
+t = FIELD_DP64(t, ID_AA64ISAR0, AES, 0);
+t = FIELD_DP64(t,
As of now, cryptographic instructions ISAR fields are never cleared so
we can end up with a cpu with cryptographic instructions but no
floating-point/neon instructions which is impossible according to ARM
specifications.
In QEMU, we have 3 kinds of cpus regarding cryptographic instructions:
+ no
