Re: [PATCH] target/mips: enable GINVx support for I6400 and I6500

2023-07-10 Thread Philippe Mathieu-Daudé
On 30/6/23 09:28, Marcin Nowakowski wrote: GINVI and GINVT operations are supported on MIPS I6400 and I6500 cores, so indicate that properly in CP0.Config5 register bits [16:15]. Signed-off-by: Marcin Nowakowski --- target/mips/cpu-defs.c.inc | 4 ++-- 1 file changed, 2 insertions(+), 2

Re: [PATCH] target/mips: enable GINVx support for I6400 and I6500

2023-07-10 Thread Philippe Mathieu-Daudé
On 10/7/23 14:58, Jiaxun Yang wrote: 在 2023/6/30 15:28, Marcin Nowakowski 写道: GINVI and GINVT operations are supported on MIPS I6400 and I6500 cores, so indicate that properly in CP0.Config5 register bits [16:15]. Signed-off-by: Marcin Nowakowski VZ is unimplemented in TCG so perhaps we

Re: [PATCH] target/mips: enable GINVx support for I6400 and I6500

2023-07-10 Thread Jiaxun Yang
在 2023/6/30 15:28, Marcin Nowakowski 写道: GINVI and GINVT operations are supported on MIPS I6400 and I6500 cores, so indicate that properly in CP0.Config5 register bits [16:15]. Signed-off-by: Marcin Nowakowski VZ is unimplemented in TCG so perhaps we should leave them as not supported?

Re: [PATCH] target/mips: enable GINVx support for I6400 and I6500

2023-07-10 Thread Philippe Mathieu-Daudé
On 30/6/23 09:28, Marcin Nowakowski wrote: GINVI and GINVT operations are supported on MIPS I6400 and I6500 cores, so indicate that properly in CP0.Config5 register bits [16:15]. Signed-off-by: Marcin Nowakowski --- target/mips/cpu-defs.c.inc | 4 ++-- 1 file changed, 2 insertions(+), 2

[PATCH] target/mips: enable GINVx support for I6400 and I6500

2023-06-30 Thread Marcin Nowakowski
GINVI and GINVT operations are supported on MIPS I6400 and I6500 cores, so indicate that properly in CP0.Config5 register bits [16:15]. Signed-off-by: Marcin Nowakowski --- target/mips/cpu-defs.c.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git