Re: [PATCH] target/riscv: Check the correct exception cause in vector GDB stub

On Sun, Sep 18, 2022 at 6:29 PM wrote: > > From: Frank Chang > > After RISCVException enum is introduced, riscv_csrrw_debug() returns > RISCV_EXCP_NONE to indicate there's no error. RISC-V vector GDB stub > should check the result against RISCV_EXCP_NONE instead of value 0. > Otherwise, 'E14'

Re: [PATCH] target/riscv: Check the correct exception cause in vector GDB stub

On Sun, Sep 18, 2022 at 6:29 PM wrote: > > From: Frank Chang > > After RISCVException enum is introduced, riscv_csrrw_debug() returns > RISCV_EXCP_NONE to indicate there's no error. RISC-V vector GDB stub > should check the result against RISCV_EXCP_NONE instead of value 0. > Otherwise, 'E14'

Re: [PATCH] target/riscv: Check the correct exception cause in vector GDB stub

Reviewed-by: LIU Zhiwei Zhiwei On 2022/9/18 16:32, frank.ch...@sifive.com wrote: From: Frank Chang After RISCVException enum is introduced, riscv_csrrw_debug() returns RISCV_EXCP_NONE to indicate there's no error. RISC-V vector GDB stub should check the result against RISCV_EXCP_NONE

[PATCH] target/riscv: Check the correct exception cause in vector GDB stub

From: Frank Chang After RISCVException enum is introduced, riscv_csrrw_debug() returns RISCV_EXCP_NONE to indicate there's no error. RISC-V vector GDB stub should check the result against RISCV_EXCP_NONE instead of value 0. Otherwise, 'E14' packet would be incorrectly reported for vector CSRs