Re: [PATCH] target/riscv: line up all of the registers in the info register dump

On Sat, Oct 9, 2021 at 3:51 PM Travis Geiselbrecht wrote: > > Ensure the columns for all of the register names and values line up. > No functional change, just a minor tweak to the output. > > Signed-off-by: Travis Geiselbrecht Thanks! Applied to riscv-to-apply.next Alistair

Re: [PATCH] target/riscv: line up all of the registers in the info register dump

On Sat, Oct 9, 2021 at 3:51 PM Travis Geiselbrecht wrote: > > Ensure the columns for all of the register names and values line up. > No functional change, just a minor tweak to the output. > > Signed-off-by: Travis Geiselbrecht Reviewed-by: Alistair Francis Alistair > --- >

[PATCH] target/riscv: line up all of the registers in the info register dump

Ensure the columns for all of the register names and values line up. No functional change, just a minor tweak to the output. Signed-off-by: Travis Geiselbrecht --- target/riscv/cpu.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu.c