Re: [PATCH] target/riscv: trans_rvv: Avoid assert for RV32 and e64

2022-06-09 Thread Alistair Francis 
On Thu, Jun 9, 2022 at 9:47 AM Alistair Francis
 wrote:
>
> From: Alistair Francis 
>
> When running a 32-bit guest, with a e64 vmv.v.x and vl_eq_vlmax set to
> true the `tcg_debug_assert(vece <= MO_32)` will be triggered inside
> tcg_gen_gvec_dup_i32().
>
> This patch checks that condition and instead uses tcg_gen_gvec_dup_i64()
> is required.
>
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1028
> Suggested-by: Robert Bu 
> Signed-off-by: Alistair Francis 

Thanks!

Applied to riscv-to-apply.next

Alistair

> ---
>  target/riscv/insn_trans/trans_rvv.c.inc | 12 ++--
>  1 file changed, 10 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc 
> b/target/riscv/insn_trans/trans_rvv.c.inc
> index 391c61fe93..6b27d8e91e 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -2097,8 +2097,16 @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x 
> *a)
>  s1 = get_gpr(s, a->rs1, EXT_SIGN);
>
>  if (s->vl_eq_vlmax) {
> -tcg_gen_gvec_dup_tl(s->sew, vreg_ofs(s, a->rd),
> -MAXSZ(s), MAXSZ(s), s1);
> +if (get_xl(s) == MXL_RV32 && s->sew == MO_64) {
> +TCGv_i64 s1_i64 = tcg_temp_new_i64();
> +tcg_gen_ext_tl_i64(s1_i64, s1);
> +tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd),
> + MAXSZ(s), MAXSZ(s), s1_i64);
> +tcg_temp_free_i64(s1_i64);
> +} else {
> +tcg_gen_gvec_dup_tl(s->sew, vreg_ofs(s, a->rd),
> +MAXSZ(s), MAXSZ(s), s1);
> +}
>  } else {
>  TCGv_i32 desc;
>  TCGv_i64 s1_i64 = tcg_temp_new_i64();
> --
> 2.36.1
>

Re: [PATCH] target/riscv: trans_rvv: Avoid assert for RV32 and e64

2022-06-09 Thread Richard Henderson 

On 6/8/22 16:47, Alistair Francis wrote:

From: Alistair Francis 

When running a 32-bit guest, with a e64 vmv.v.x and vl_eq_vlmax set to
true the `tcg_debug_assert(vece <= MO_32)` will be triggered inside
tcg_gen_gvec_dup_i32().

This patch checks that condition and instead uses tcg_gen_gvec_dup_i64()
is required.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1028
Suggested-by: Robert Bu 
Signed-off-by: Alistair Francis 


Reviewed-by: Richard Henderson 


r~


---
  target/riscv/insn_trans/trans_rvv.c.inc | 12 ++--
  1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc 
b/target/riscv/insn_trans/trans_rvv.c.inc
index 391c61fe93..6b27d8e91e 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2097,8 +2097,16 @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x 
*a)
  s1 = get_gpr(s, a->rs1, EXT_SIGN);
  
  if (s->vl_eq_vlmax) {

-tcg_gen_gvec_dup_tl(s->sew, vreg_ofs(s, a->rd),
-MAXSZ(s), MAXSZ(s), s1);
+if (get_xl(s) == MXL_RV32 && s->sew == MO_64) {
+TCGv_i64 s1_i64 = tcg_temp_new_i64();
+tcg_gen_ext_tl_i64(s1_i64, s1);
+tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd),
+ MAXSZ(s), MAXSZ(s), s1_i64);
+tcg_temp_free_i64(s1_i64);
+} else {
+tcg_gen_gvec_dup_tl(s->sew, vreg_ofs(s, a->rd),
+MAXSZ(s), MAXSZ(s), s1);
+}
  } else {
  TCGv_i32 desc;
  TCGv_i64 s1_i64 = tcg_temp_new_i64();

[PATCH] target/riscv: trans_rvv: Avoid assert for RV32 and e64

2022-06-08 Thread Alistair Francis 
From: Alistair Francis 

When running a 32-bit guest, with a e64 vmv.v.x and vl_eq_vlmax set to
true the `tcg_debug_assert(vece <= MO_32)` will be triggered inside
tcg_gen_gvec_dup_i32().

This patch checks that condition and instead uses tcg_gen_gvec_dup_i64()
is required.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1028
Suggested-by: Robert Bu 
Signed-off-by: Alistair Francis 
---
 target/riscv/insn_trans/trans_rvv.c.inc | 12 ++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc 
b/target/riscv/insn_trans/trans_rvv.c.inc
index 391c61fe93..6b27d8e91e 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2097,8 +2097,16 @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x 
*a)
 s1 = get_gpr(s, a->rs1, EXT_SIGN);
 
 if (s->vl_eq_vlmax) {
-tcg_gen_gvec_dup_tl(s->sew, vreg_ofs(s, a->rd),
-MAXSZ(s), MAXSZ(s), s1);
+if (get_xl(s) == MXL_RV32 && s->sew == MO_64) {
+TCGv_i64 s1_i64 = tcg_temp_new_i64();
+tcg_gen_ext_tl_i64(s1_i64, s1);
+tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd),
+ MAXSZ(s), MAXSZ(s), s1_i64);
+tcg_temp_free_i64(s1_i64);
+} else {
+tcg_gen_gvec_dup_tl(s->sew, vreg_ofs(s, a->rd),
+MAXSZ(s), MAXSZ(s), s1);
+}
 } else {
 TCGv_i32 desc;
 TCGv_i64 s1_i64 = tcg_temp_new_i64();
-- 
2.36.1