Re: [PATCH] target/sh4: add missing CHECK_NOT_DELAY_SLOT
On Mon, 08 Apr 2024 00:07:05 +0900,
Zack Buhman wrote:
>
> CHECK_NOT_DELAY_SLOT is correctly applied to the branch-related
> instructions, but not to the PC-relative mov* instructions.
>
> I verified the existence of an illegal slot exception on a SH7091 when
> any of these instructions are attempted inside a delay slot.
>
> This also matches the behavior described in the SH-4 ISA manual.
>
> Signed-off-by: Zack Buhman
> ---
> target/sh4/translate.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/target/sh4/translate.c b/target/sh4/translate.c
> index 6643c14dde..ebb6c901bf 100644
> --- a/target/sh4/translate.c
> +++ b/target/sh4/translate.c
> @@ -523,6 +523,7 @@ static void _decode_opc(DisasContext * ctx)
> tcg_gen_movi_i32(REG(B11_8), B7_0s);
> return;
> case 0x9000: /* mov.w @(disp,PC),Rn */
> +CHECK_NOT_DELAY_SLOT
> {
> TCGv addr = tcg_constant_i32(ctx->base.pc_next + 4 + B7_0 * 2);
> tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx,
> @@ -530,6 +531,7 @@ static void _decode_opc(DisasContext * ctx)
> }
> return;
> case 0xd000: /* mov.l @(disp,PC),Rn */
> +CHECK_NOT_DELAY_SLOT
> {
> TCGv addr = tcg_constant_i32((ctx->base.pc_next + 4 + B7_0 * 4)
> & ~3);
> tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx,
> @@ -1236,6 +1238,7 @@ static void _decode_opc(DisasContext * ctx)
> }
> return;
> case 0xc700: /* mova @(disp,PC),R0 */
> +CHECK_NOT_DELAY_SLOT
> tcg_gen_movi_i32(REG(0), ((ctx->base.pc_next & 0xfffc) +
>4 + B7_0 * 4) & ~3);
> return;
> --
> 2.41.0
>
That's what the documentation said.
> If a PC-relative load instruction is executed in a delay slot,
> an illegal slot instruction exception will be generated.
Reviewed-by: Yoshinori Sato
--
Yosinori Sato
Re: [PATCH] target/sh4: add missing CHECK_NOT_DELAY_SLOT
On 4/7/24 05:07, Zack Buhman wrote: CHECK_NOT_DELAY_SLOT is correctly applied to the branch-related instructions, but not to the PC-relative mov* instructions. I verified the existence of an illegal slot exception on a SH7091 when any of these instructions are attempted inside a delay slot. This also matches the behavior described in the SH-4 ISA manual. Signed-off-by: Zack Buhman --- target/sh4/translate.c | 3 +++ 1 file changed, 3 insertions(+) Reviewed-by: Richard Henderson r~
[PATCH] target/sh4: add missing CHECK_NOT_DELAY_SLOT
CHECK_NOT_DELAY_SLOT is correctly applied to the branch-related
instructions, but not to the PC-relative mov* instructions.
I verified the existence of an illegal slot exception on a SH7091 when
any of these instructions are attempted inside a delay slot.
This also matches the behavior described in the SH-4 ISA manual.
Signed-off-by: Zack Buhman
---
target/sh4/translate.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index 6643c14dde..ebb6c901bf 100644
--- a/target/sh4/translate.c
+++ b/target/sh4/translate.c
@@ -523,6 +523,7 @@ static void _decode_opc(DisasContext * ctx)
tcg_gen_movi_i32(REG(B11_8), B7_0s);
return;
case 0x9000: /* mov.w @(disp,PC),Rn */
+CHECK_NOT_DELAY_SLOT
{
TCGv addr = tcg_constant_i32(ctx->base.pc_next + 4 + B7_0 * 2);
tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx,
@@ -530,6 +531,7 @@ static void _decode_opc(DisasContext * ctx)
}
return;
case 0xd000: /* mov.l @(disp,PC),Rn */
+CHECK_NOT_DELAY_SLOT
{
TCGv addr = tcg_constant_i32((ctx->base.pc_next + 4 + B7_0 * 4) &
~3);
tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx,
@@ -1236,6 +1238,7 @@ static void _decode_opc(DisasContext * ctx)
}
return;
case 0xc700: /* mova @(disp,PC),R0 */
+CHECK_NOT_DELAY_SLOT
tcg_gen_movi_i32(REG(0), ((ctx->base.pc_next & 0xfffc) +
4 + B7_0 * 4) & ~3);
return;
--
2.41.0
