On 9/27/21 1:36 AM, Philippe Mathieu-Daudé wrote:
There are not 64 registers, so this is incorrect.
Currently there are 32 registers, but I was looking at this draft:
https://five-embeddev.com/riscv-v-spec/draft/v-spec.html#_vector_registers
"The vector extension adds 32 architectural vector
On 9/27/21 01:06, Richard Henderson wrote:
> On 9/26/21 5:39 PM, Philippe Mathieu-Daudé wrote:
>> The tcg_target_call_clobber_regs variable is of type TCGRegSet,
>> which is unsigned and might be 64-bit wide. By initializing it
>> as unsigned type, only 32-bit are set. Currently the RISCV TCG
>>
On 9/26/21 5:39 PM, Philippe Mathieu-Daudé wrote:
The tcg_target_call_clobber_regs variable is of type TCGRegSet,
which is unsigned and might be 64-bit wide. By initializing it
as unsigned type, only 32-bit are set. Currently the RISCV TCG
backend only uses 32 registers, so this is not a
The tcg_target_call_clobber_regs variable is of type TCGRegSet,
which is unsigned and might be 64-bit wide. By initializing it
as unsigned type, only 32-bit are set. Currently the RISCV TCG
backend only uses 32 registers, so this is not a problem.
However if more register were to be implemented
