On 05/28/21 01:06, Haozhong Zhang wrote:
> The current implementation leaves 0 in the maximum link width (MLW)
> and speed (MLS) fields of the PCI_EXP_LNKCAP register of a xio3130
> downstream port device. As a consequence, when that downstream port
> negotiates the link width and speed with its
The current implementation leaves 0 in the maximum link width (MLW)
and speed (MLS) fields of the PCI_EXP_LNKCAP register of a xio3130
downstream port device. As a consequence, when that downstream port
negotiates the link width and speed with its downstream device, 0 will
be used and filled in
