Hello, I discovered a couple of bugs in the watchdog while testing a tool to poke Aspeed BMCs over their various AHB bridges. The immediate observation was that the model for the 2500 wasn't signalling use of the fixed 1MHz clock, which is resolved in the first patch. The other observation was that sequential writes to control weren't sticking if the enable bit wasn't toggled, which is fixed in the second patch.
Please review. Andrew Andrew Jeffery (2): watchdog: aspeed: Sanitize control register values watchdog: aspeed: Fix sequential control writes hw/watchdog/wdt_aspeed.c | 26 ++++++++++++++++++++++++-- include/hw/watchdog/wdt_aspeed.h | 1 + 2 files changed, 25 insertions(+), 2 deletions(-) -- 2.30.2
