From: Frank Chang <frank.ch...@sifive.com>
This patchset refactors RISC-V Debug support to allow more types of
triggers to be extended.
The initial support of type 6 trigger, which is similar to type 2
trigger with additional functionality, is also introduced in this
patchset.
Frank Chang (9):
target/riscv: debug: Determine the trigger type from tdata1.type
target/riscv: debug: Introduce build_tdata1() to build tdata1 register
content
target/riscv: debug: Introduce tdata1, tdata2, and tdata3 CSRs
target/riscv: debug: Restrict the range of tselect value can be
written
target/riscv: debug: Introduce tinfo CSR
target/riscv: debug: Create common trigger actions function
target/riscv: debug: Check VU/VS modes for type 2 trigger
target/riscv: debug: Return 0 if previous value written to tselect >=
number of triggers
target/riscv: debug: Add initial support of type 6 trigger
target/riscv/cpu.h | 7 +-
target/riscv/cpu_bits.h | 1 +
target/riscv/csr.c | 10 +-
target/riscv/debug.c | 483 ++++++++++++++++++++++++++++++++--------
target/riscv/debug.h | 55 +++--
target/riscv/machine.c | 20 +-
6 files changed, 445 insertions(+), 131 deletions(-)
--
2.36.1
