On 2020/6/2 上午12:47, Andrew Melnichenko wrote:
As I understand it, the e1000e.c was implemented by 82574L
spec(https://www.intel.com/content/dam/doc/datasheet/82574l-gbe-controller-datasheet.pdf).
In the same spec there is 10.2.4 paragraph which provides more details
when ICR should be
As I understand it, the e1000e.c was implemented by 82574L spec(
https://www.intel.com/content/dam/doc/datasheet/82574l-gbe-controller-datasheet.pdf
).
In the same spec there is 10.2.4 paragraph which provides more details when
ICR should be cleared.
> • Case 1 - Interrupt Mask register equals
On 2020/5/29 下午3:18, Jason Wang wrote:
On 2020/5/13 下午7:31, and...@daynix.com wrote:
From: Andrew Melnychenko
Buglink: https://bugzilla.redhat.com/show_bug.cgi?id=1707441
Added ICR clearing if there is IMS bit - according to the note by
section 13.3.27 of the 8257X developers manual.
On 2020/5/13 下午7:31, and...@daynix.com wrote:
From: Andrew Melnychenko
Buglink: https://bugzilla.redhat.com/show_bug.cgi?id=1707441
Added ICR clearing if there is IMS bit - according to the note by
section 13.3.27 of the 8257X developers manual.
Signed-off-by: Andrew Melnychenko
---
From: Andrew Melnychenko
Buglink: https://bugzilla.redhat.com/show_bug.cgi?id=1707441
Added ICR clearing if there is IMS bit - according to the note by
section 13.3.27 of the 8257X developers manual.
Signed-off-by: Andrew Melnychenko
---
hw/net/e1000e_core.c | 10 ++
From: Andrew Melnychenko
Buglink: https://bugzilla.redhat.com/show_bug.cgi?id=1707441
Added ICR clearing if there is IMS bit - according to the note by
section 13.3.27 of the 8257X developers manual.
Signed-off-by: Andrew Melnychenko
---
hw/net/e1000e_core.c | 9 +
hw/net/trace-events
