Re: [PATCH 1/1] target/riscv: Fix vsip vsie CSR ops in M and HS mode

On 5/28/21 6:19 AM, Alistair Francis wrote: On Thu, May 27, 2021 at 7:01 PM LIU Zhiwei wrote: When V=1, instructions that normally read or modify a supervisor CSR shall instead access the corresponding VS CSR. And the VS CSRs can be accessed as themselves from M-mode or HS-mode. In M and HS

Re: [PATCH 1/1] target/riscv: Fix vsip vsie CSR ops in M and HS mode

On Thu, May 27, 2021 at 7:01 PM LIU Zhiwei wrote: > > When V=1, instructions that normally read or modify a supervisor CSR > shall instead access the corresponding VS CSR. And the VS CSRs can be > accessed as themselves from M-mode or HS-mode. > > In M and HS mode, VSIP or VSIE should be written

[PATCH 1/1] target/riscv: Fix vsip vsie CSR ops in M and HS mode

When V=1, instructions that normally read or modify a supervisor CSR shall instead access the corresponding VS CSR. And the VS CSRs can be accessed as themselves from M-mode or HS-mode. In M and HS mode, VSIP or VSIE should be written normally instead of shift by 1. Signed-off-by: LIU Zhiwei