Re: [PATCH 11/19] target/mips: Extract common helpers from helper.c to common_helper.c

[Philippe Mathieu-Daudé]

On 12/14/20 3:51 PM, 罗勇刚(Yonggang Luo) wrote:
> On Wed, Dec 9, 2020 at 6:09 AM Richard Henderson
> mailto:richard.hender...@linaro.org>> wrote:
>>
>> On 12/6/20 5:39 PM, Philippe Mathieu-Daudé wrote:
>> > The rest of helper.c is TLB related. Extract the non TLB
>> > specific functions to a new file, so we can rename helper.c
>> > as tlb_helper.c in the next commit.
>> >
>> > Signed-off-by: Philippe Mathieu-Daudé  >
>> > ---
>> > Any better name? xxx_helper.c are usually TCG helpers.
>>
>> *shrug* perhaps cpu_common.c, no "helper" at all?
>> Perhaps just move these bits to cpu.c?
>>
>>
>> r~
>>
> Does these are general cpu bits or misp_cpu bits?
> if only misp cpu related, prefer misp_cpu.c
> or cpu.c under misp folder.

Yes, as the patch subject prefix implies, this is a change
local to the target/mips/ directory.

Regards,

Phil.

Re: [PATCH 11/19] target/mips: Extract common helpers from helper.c to common_helper.c

[Yonggang Luo]

On Wed, Dec 9, 2020 at 6:09 AM Richard Henderson <
richard.hender...@linaro.org> wrote:
>
> On 12/6/20 5:39 PM, Philippe Mathieu-Daudé wrote:
> > The rest of helper.c is TLB related. Extract the non TLB
> > specific functions to a new file, so we can rename helper.c
> > as tlb_helper.c in the next commit.
> >
> > Signed-off-by: Philippe Mathieu-Daudé 
> > ---
> > Any better name? xxx_helper.c are usually TCG helpers.
>
> *shrug* perhaps cpu_common.c, no "helper" at all?
> Perhaps just move these bits to cpu.c?
>
>
> r~
>
Does these are general cpu bits or misp_cpu bits?
if only misp cpu related, prefer misp_cpu.c
or cpu.c under misp folder.

--
 此致
礼
罗勇刚
Yours
sincerely,
Yonggang Luo

Re: [PATCH 11/19] target/mips: Extract common helpers from helper.c to common_helper.c

[Philippe Mathieu-Daudé]

On 12/8/20 11:06 PM, Richard Henderson wrote:
> On 12/6/20 5:39 PM, Philippe Mathieu-Daudé wrote:
>> The rest of helper.c is TLB related. Extract the non TLB
>> specific functions to a new file, so we can rename helper.c
>> as tlb_helper.c in the next commit.
>>
>> Signed-off-by: Philippe Mathieu-Daudé 
>> ---
>> Any better name? xxx_helper.c are usually TCG helpers.
> 
> *shrug* perhaps cpu_common.c, no "helper" at all?
> Perhaps just move these bits to cpu.c?

Sounds good, thanks :)

Re: [PATCH 11/19] target/mips: Extract common helpers from helper.c to common_helper.c

[Richard Henderson]

On 12/6/20 5:39 PM, Philippe Mathieu-Daudé wrote:
> The rest of helper.c is TLB related. Extract the non TLB
> specific functions to a new file, so we can rename helper.c
> as tlb_helper.c in the next commit.
> 
> Signed-off-by: Philippe Mathieu-Daudé 
> ---
> Any better name? xxx_helper.c are usually TCG helpers.

*shrug* perhaps cpu_common.c, no "helper" at all?
Perhaps just move these bits to cpu.c?


r~

[PATCH 11/19] target/mips: Extract common helpers from helper.c to common_helper.c

[Philippe Mathieu-Daudé]

The rest of helper.c is TLB related. Extract the non TLB
specific functions to a new file, so we can rename helper.c
as tlb_helper.c in the next commit.

Signed-off-by: Philippe Mathieu-Daudé 
---
Any better name? xxx_helper.c are usually TCG helpers.
---
 target/mips/common_helper.c | 178 
 target/mips/helper.c| 152 --
 target/mips/meson.build |   1 +
 3 files changed, 179 insertions(+), 152 deletions(-)
 create mode 100644 target/mips/common_helper.c

diff --git a/target/mips/common_helper.c b/target/mips/common_helper.c
new file mode 100644
index 000..07c947ecc55
--- /dev/null
+++ b/target/mips/common_helper.c
@@ -0,0 +1,178 @@
+/*
+ *  MIPS emulation helpers for qemu.
+ *
+ *  Copyright (c) 2004-2005 Jocelyn Mayer
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see .
+ */
+#include "qemu/osdep.h"
+
+#include "cpu.h"
+#include "internal.h"
+#include "exec/exec-all.h"
+#include "exec/log.h"
+
+#if !defined(CONFIG_USER_ONLY)
+
+/* Called for updates to CP0_Status.  */
+void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc)
+{
+int32_t tcstatus, *tcst;
+uint32_t v = cpu->CP0_Status;
+uint32_t cu, mx, asid, ksu;
+uint32_t mask = ((1 << CP0TCSt_TCU3)
+   | (1 << CP0TCSt_TCU2)
+   | (1 << CP0TCSt_TCU1)
+   | (1 << CP0TCSt_TCU0)
+   | (1 << CP0TCSt_TMX)
+   | (3 << CP0TCSt_TKSU)
+   | (0xff << CP0TCSt_TASID));
+
+cu = (v >> CP0St_CU0) & 0xf;
+mx = (v >> CP0St_MX) & 0x1;
+ksu = (v >> CP0St_KSU) & 0x3;
+asid = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
+
+tcstatus = cu << CP0TCSt_TCU0;
+tcstatus |= mx << CP0TCSt_TMX;
+tcstatus |= ksu << CP0TCSt_TKSU;
+tcstatus |= asid;
+
+if (tc == cpu->current_tc) {
+tcst = &cpu->active_tc.CP0_TCStatus;
+} else {
+tcst = &cpu->tcs[tc].CP0_TCStatus;
+}
+
+*tcst &= ~mask;
+*tcst |= tcstatus;
+compute_hflags(cpu);
+}
+
+void cpu_mips_store_status(CPUMIPSState *env, target_ulong val)
+{
+uint32_t mask = env->CP0_Status_rw_bitmask;
+target_ulong old = env->CP0_Status;
+
+if (env->insn_flags & ISA_MIPS32R6) {
+bool has_supervisor = extract32(mask, CP0St_KSU, 2) == 0x3;
+#if defined(TARGET_MIPS64)
+uint32_t ksux = (1 << CP0St_KX) & val;
+ksux |= (ksux >> 1) & val; /* KX = 0 forces SX to be 0 */
+ksux |= (ksux >> 1) & val; /* SX = 0 forces UX to be 0 */
+val = (val & ~(7 << CP0St_UX)) | ksux;
+#endif
+if (has_supervisor && extract32(val, CP0St_KSU, 2) == 0x3) {
+mask &= ~(3 << CP0St_KSU);
+}
+mask &= ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val);
+}
+
+env->CP0_Status = (old & ~mask) | (val & mask);
+#if defined(TARGET_MIPS64)
+if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) {
+/* Access to at least one of the 64-bit segments has been disabled */
+tlb_flush(env_cpu(env));
+}
+#endif
+if (env->CP0_Config3 & (1 << CP0C3_MT)) {
+sync_c0_status(env, env, env->current_tc);
+} else {
+compute_hflags(env);
+}
+}
+
+void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val)
+{
+uint32_t mask = 0x00C00300;
+uint32_t old = env->CP0_Cause;
+int i;
+
+if (env->insn_flags & ISA_MIPS32R2) {
+mask |= 1 << CP0Ca_DC;
+}
+if (env->insn_flags & ISA_MIPS32R6) {
+mask &= ~((1 << CP0Ca_WP) & val);
+}
+
+env->CP0_Cause = (env->CP0_Cause & ~mask) | (val & mask);
+
+if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) {
+if (env->CP0_Cause & (1 << CP0Ca_DC)) {
+cpu_mips_stop_count(env);
+} else {
+cpu_mips_start_count(env);
+}
+}
+
+/* Set/reset software interrupts */
+for (i = 0 ; i < 2 ; i++) {
+if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) {
+cpu_mips_soft_irq(env, i, env->CP0_Cause & (1 << (CP0Ca_IP + i)));
+}
+}
+}
+
+#endif /* !CONFIG_USER_ONLY */
+
+target_ulong exception_resume_pc(CPUMIPSState *env)
+{
+target_ulong bad_pc;
+target_ulong isa_mode;
+
+isa_mode = !!(env->hflags & MIPS_HFLAG_M16);
+bad_pc = env->active_tc.PC | isa_mode;
+if (env->hflags & MIPS_HFLAG_BMAS