On 12/18/20 12:37 AM, remi.denis.courm...@huawei.com wrote: > @@ -3297,7 +3301,7 @@ typedef ARMCPU ArchCPU; > * We put flags which are shared between 32 and 64 bit mode at the top > * of the word, and flags which apply to only one mode at the bottom. > * > - * 31 20 18 14 9 0 > + * 31 20 19 14 9 0 > * +--------------+-----+-----+----------+--------------+ > * | | | TBFLAG_A32 | | > * | | +-----+----------+ TBFLAG_AM32 | > @@ -3346,6 +3350,7 @@ FIELD(TBFLAG_A32, HSTR_ACTIVE, 16, 1) > * the same thing as the current security state of the processor! > */ > FIELD(TBFLAG_A32, NS, 17, 1) > +FIELD(TBFLAG_A32, EEL2, 18, 1)
Note that via other in-flight patch sets we have run out of bits here. I've rearranged them in https://patchew.org/QEMU/20210111190113.303726-1-richard.hender...@linaro.org/ This should be nothing but a minor confict to fix up. r~
