Re: [PATCH 3/3] hw/riscv/spike: Allow more than one CPUs

2020-02-14 Thread Alistair Francis
On Thu, Feb 13, 2020 at 11:24 PM Anup Patel wrote: > > Currently, the upstream Spike ISA simulator allows more than > one CPUs so we update QEMU Spike machine on similar lines to > allow more than one CPUs. > > The maximum number of CPUs for QEMU Spike machine is kept > same as QEMU Virt machine.

[PATCH 3/3] hw/riscv/spike: Allow more than one CPUs

2020-02-13 Thread Anup Patel
Currently, the upstream Spike ISA simulator allows more than one CPUs so we update QEMU Spike machine on similar lines to allow more than one CPUs. The maximum number of CPUs for QEMU Spike machine is kept same as QEMU Virt machine. Signed-off-by: Anup Patel --- hw/riscv/spike.c | 2 +- 1 file