Re: [PATCH 3/8] accel/tcg: Support TCG_TARGET_SIGNED_ADDR32 for softmmu

2021-10-11 Thread Richard Henderson
On 10/10/21 9:30 PM, WANG Xuerui wrote: @@ -92,6 +93,9 @@ static inline size_t sizeof_tlb(CPUTLBDescFast *fast) static inline uintptr_t g2h_tlbe(const CPUTLBEntry *tlb, target_ulong gaddr) { +if (TCG_TARGET_SIGNED_ADDR32 && TARGET_LONG_BITS == 32) { It seems this branch's direction

Re: [PATCH 3/8] accel/tcg: Support TCG_TARGET_SIGNED_ADDR32 for softmmu

2021-10-10 Thread WANG Xuerui
Hi Richard, On 2021/10/11 01:43, Richard Henderson wrote: > When TCG_TARGET_SIGNED_ADDR32 is set, adjust the tlb addend to > allow the 32-bit guest address to be sign extended within the > 64-bit host register instead of zero extended. > > This will simplify tcg hosts like MIPS, RISC-V, and

[PATCH 3/8] accel/tcg: Support TCG_TARGET_SIGNED_ADDR32 for softmmu

2021-10-10 Thread Richard Henderson
When TCG_TARGET_SIGNED_ADDR32 is set, adjust the tlb addend to allow the 32-bit guest address to be sign extended within the 64-bit host register instead of zero extended. This will simplify tcg hosts like MIPS, RISC-V, and LoongArch, which naturally sign-extend 32-bit values, in contrast to