Re: [PATCH 4/4] riscv: Add semihosting support [v11]
Alistair Francis writes: >> +return (nr == TARGET_SYS_EXIT_EXTENDED || sizeof(target_ulong) == 0); > > How would sizeof(target_ulong) == 0 ? Oops. This is supposed to be 8, not 0. And those look very similar on the screen. I caught this myself a couple of weeks ago but forgot to send out a new version here. Sorry! From a6cb1a52a6c2404a9bdc22bb5e00bccb65ab0730 Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Mon, 26 Oct 2020 12:20:01 -0700 Subject: [PATCH 4/4] riscv: Add semihosting support [v12] Adapt the arm semihosting support code for RISCV. This implementation is based on the standard for RISC-V semihosting version 0.2 as documented in https://github.com/riscv/riscv-semihosting-spec/releases/tag/0.2 Signed-off-by: Keith Packard --- v2: Update PC after exception is handled to follow change in the ARM version for SYS_READC v3: Disallow semihosting in user mode; report a regular breakpoint in that case. v4: Fix errors reported by checkpatch v5: Reference current RISC-V semihosting specification v6: Add support for semihosting in riscv64-linux-user and riscv32-linux-user v7: Add meson build support v8: Fix errors reported by checkpatch that crept in. v9: Changes suggested by Alistair Francis : Don't add me to the MAINTAINERS file. Remove duplicate #include in target/riscv/cpu.h Reference RISC-V semihosting spec in target/riscv/riscv-semi.c v10: Use common semihosting implementation instead of a separate copy. Make sure addresses of the three breakpoint-signaling instructions all lie within the same page. Change suggested by Richard Henderson v11: Use CONFIG_ARM_COMPATIBLE_SEMIHOSTING v12: Fix bug in SYS_EXIT support on rv64 --- default-configs/devices/riscv32-softmmu.mak | 2 + default-configs/devices/riscv64-softmmu.mak | 2 + .../targets/riscv32-linux-user.mak| 1 + .../targets/riscv64-linux-user.mak| 1 + hw/semihosting/common-semi.c | 51 ++- hw/semihosting/common-semi.h | 5 +- linux-user/qemu.h | 4 +- linux-user/semihost.c | 8 +-- qemu-options.hx | 10 ++-- target/riscv/cpu_bits.h | 1 + target/riscv/cpu_helper.c | 10 .../riscv/insn_trans/trans_privileged.c.inc | 37 +- target/riscv/translate.c | 11 13 files changed, 131 insertions(+), 12 deletions(-) diff --git a/default-configs/devices/riscv32-softmmu.mak b/default-configs/devices/riscv32-softmmu.mak index 94a236c9c2..d847bd5692 100644 --- a/default-configs/devices/riscv32-softmmu.mak +++ b/default-configs/devices/riscv32-softmmu.mak @@ -3,6 +3,8 @@ # Uncomment the following lines to disable these optional devices: # #CONFIG_PCI_DEVICES=n +CONFIG_SEMIHOSTING=y +CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y # Boards: # diff --git a/default-configs/devices/riscv64-softmmu.mak b/default-configs/devices/riscv64-softmmu.mak index 76b6195648..d5eec75f05 100644 --- a/default-configs/devices/riscv64-softmmu.mak +++ b/default-configs/devices/riscv64-softmmu.mak @@ -3,6 +3,8 @@ # Uncomment the following lines to disable these optional devices: # #CONFIG_PCI_DEVICES=n +CONFIG_SEMIHOSTING=y +CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y # Boards: # diff --git a/default-configs/targets/riscv32-linux-user.mak b/default-configs/targets/riscv32-linux-user.mak index dfb259e8aa..6a9d1b1bc1 100644 --- a/default-configs/targets/riscv32-linux-user.mak +++ b/default-configs/targets/riscv32-linux-user.mak @@ -2,3 +2,4 @@ TARGET_ARCH=riscv32 TARGET_BASE_ARCH=riscv TARGET_ABI_DIR=riscv TARGET_XML_FILES= gdb-xml/riscv-32bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-32bit-csr.xml gdb-xml/riscv-32bit-virtual.xml +CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y diff --git a/default-configs/targets/riscv64-linux-user.mak b/default-configs/targets/riscv64-linux-user.mak index b13895f3b0..0a92849a1b 100644 --- a/default-configs/targets/riscv64-linux-user.mak +++ b/default-configs/targets/riscv64-linux-user.mak @@ -2,3 +2,4 @@ TARGET_ARCH=riscv64 TARGET_BASE_ARCH=riscv TARGET_ABI_DIR=riscv TARGET_XML_FILES= gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-64bit-csr.xml gdb-xml/riscv-64bit-virtual.xml +CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y diff --git a/hw/semihosting/common-semi.c b/hw/semihosting/common-semi.c index c77fb21bec..f8c5d04732 100644 --- a/hw/semihosting/common-semi.c +++ b/hw/semihosting/common-semi.c @@ -1,6 +1,6 @@ /* * Semihosting support for systems modeled on the Arm "Angel" - * semihosting syscalls design. + * semihosting syscalls design. This includes Arm and RISC-V processors * * Copyright (c) 2005, 2007 CodeSourcery. * Copyright (c) 2019 Linaro @@ -25,6 +25,10 @@ * ARM Semihosting is documented in: * Semihosting for AArch32 and AArch64 Release 2.0 *
Re: [PATCH 4/4] riscv: Add semihosting support [v11]
On Wed, Oct 28, 2020 at 12:04 PM Keith Packard via wrote: > > Adapt the arm semihosting support code for RISCV. This implementation > is based on the standard for RISC-V semihosting version 0.2 as > documented in > >https://github.com/riscv/riscv-semihosting-spec/releases/tag/0.2 > > Signed-off-by: Keith Packard > > --- > > v2: > Update PC after exception is handled to follow > change in the ARM version for SYS_READC > > v3: > Disallow semihosting in user mode; report a regular > breakpoint in that case. > > v4: > Fix errors reported by checkpatch > > v5: > Reference current RISC-V semihosting specification > > v6: > Add support for semihosting in riscv64-linux-user and > riscv32-linux-user > > v7: > Add meson build support > > v8: > Fix errors reported by checkpatch that crept in. > > v9: > Changes suggested by Alistair Francis : > Don't add me to the MAINTAINERS file. > Remove duplicate #include in target/riscv/cpu.h > Reference RISC-V semihosting spec in target/riscv/riscv-semi.c > > v10: > Use common semihosting implementation instead of a separate copy. > > Make sure addresses of the three breakpoint-signaling > instructions all lie within the same page. Change suggested by > Richard Henderson > > v11: > Use CONFIG_ARM_COMPATIBLE_SEMIHOSTING > --- > default-configs/devices/riscv32-softmmu.mak | 2 + > default-configs/devices/riscv64-softmmu.mak | 2 + > .../targets/riscv32-linux-user.mak| 1 + > .../targets/riscv64-linux-user.mak| 1 + > hw/semihosting/common-semi.c | 51 ++- > hw/semihosting/common-semi.h | 5 +- > linux-user/qemu.h | 4 +- > linux-user/semihost.c | 8 +-- > qemu-options.hx | 10 ++-- > target/riscv/cpu_bits.h | 1 + > target/riscv/cpu_helper.c | 10 > .../riscv/insn_trans/trans_privileged.c.inc | 37 +- > target/riscv/translate.c | 11 > 13 files changed, 131 insertions(+), 12 deletions(-) > > diff --git a/default-configs/devices/riscv32-softmmu.mak > b/default-configs/devices/riscv32-softmmu.mak > index 94a236c9c2..d847bd5692 100644 > --- a/default-configs/devices/riscv32-softmmu.mak > +++ b/default-configs/devices/riscv32-softmmu.mak > @@ -3,6 +3,8 @@ > # Uncomment the following lines to disable these optional devices: > # > #CONFIG_PCI_DEVICES=n > +CONFIG_SEMIHOSTING=y > +CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y > > # Boards: > # > diff --git a/default-configs/devices/riscv64-softmmu.mak > b/default-configs/devices/riscv64-softmmu.mak > index 76b6195648..d5eec75f05 100644 > --- a/default-configs/devices/riscv64-softmmu.mak > +++ b/default-configs/devices/riscv64-softmmu.mak > @@ -3,6 +3,8 @@ > # Uncomment the following lines to disable these optional devices: > # > #CONFIG_PCI_DEVICES=n > +CONFIG_SEMIHOSTING=y > +CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y > > # Boards: > # > diff --git a/default-configs/targets/riscv32-linux-user.mak > b/default-configs/targets/riscv32-linux-user.mak > index dfb259e8aa..6a9d1b1bc1 100644 > --- a/default-configs/targets/riscv32-linux-user.mak > +++ b/default-configs/targets/riscv32-linux-user.mak > @@ -2,3 +2,4 @@ TARGET_ARCH=riscv32 > TARGET_BASE_ARCH=riscv > TARGET_ABI_DIR=riscv > TARGET_XML_FILES= gdb-xml/riscv-32bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml > gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-32bit-csr.xml > gdb-xml/riscv-32bit-virtual.xml > +CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y > diff --git a/default-configs/targets/riscv64-linux-user.mak > b/default-configs/targets/riscv64-linux-user.mak > index b13895f3b0..0a92849a1b 100644 > --- a/default-configs/targets/riscv64-linux-user.mak > +++ b/default-configs/targets/riscv64-linux-user.mak > @@ -2,3 +2,4 @@ TARGET_ARCH=riscv64 > TARGET_BASE_ARCH=riscv > TARGET_ABI_DIR=riscv > TARGET_XML_FILES= gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml > gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-64bit-csr.xml > gdb-xml/riscv-64bit-virtual.xml > +CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y > diff --git a/hw/semihosting/common-semi.c b/hw/semihosting/common-semi.c > index c77fb21bec..8675934a71 100644 > --- a/hw/semihosting/common-semi.c > +++ b/hw/semihosting/common-semi.c > @@ -1,6 +1,6 @@ > /* > * Semihosting support for systems modeled on the Arm "Angel" > - * semihosting syscalls design. > + * semihosting syscalls design. This includes Arm and RISC-V processors > * > * Copyright (c) 2005, 2007 CodeSourcery. > * Copyright (c) 2019 Linaro > @@ -25,6 +25,10 @@ > * ARM Semihosting is documented in: > * Semihosting for AArch32 and AArch64 Release 2.0 > * https://static.docs.arm.com/100863/0200/semihosting.pdf > + * > + * RISC-V Semihosting is documented in: > +
[PATCH 4/4] riscv: Add semihosting support [v11]
Adapt the arm semihosting support code for RISCV. This implementation is based on the standard for RISC-V semihosting version 0.2 as documented in https://github.com/riscv/riscv-semihosting-spec/releases/tag/0.2 Signed-off-by: Keith Packard --- v2: Update PC after exception is handled to follow change in the ARM version for SYS_READC v3: Disallow semihosting in user mode; report a regular breakpoint in that case. v4: Fix errors reported by checkpatch v5: Reference current RISC-V semihosting specification v6: Add support for semihosting in riscv64-linux-user and riscv32-linux-user v7: Add meson build support v8: Fix errors reported by checkpatch that crept in. v9: Changes suggested by Alistair Francis : Don't add me to the MAINTAINERS file. Remove duplicate #include in target/riscv/cpu.h Reference RISC-V semihosting spec in target/riscv/riscv-semi.c v10: Use common semihosting implementation instead of a separate copy. Make sure addresses of the three breakpoint-signaling instructions all lie within the same page. Change suggested by Richard Henderson v11: Use CONFIG_ARM_COMPATIBLE_SEMIHOSTING --- default-configs/devices/riscv32-softmmu.mak | 2 + default-configs/devices/riscv64-softmmu.mak | 2 + .../targets/riscv32-linux-user.mak| 1 + .../targets/riscv64-linux-user.mak| 1 + hw/semihosting/common-semi.c | 51 ++- hw/semihosting/common-semi.h | 5 +- linux-user/qemu.h | 4 +- linux-user/semihost.c | 8 +-- qemu-options.hx | 10 ++-- target/riscv/cpu_bits.h | 1 + target/riscv/cpu_helper.c | 10 .../riscv/insn_trans/trans_privileged.c.inc | 37 +- target/riscv/translate.c | 11 13 files changed, 131 insertions(+), 12 deletions(-) diff --git a/default-configs/devices/riscv32-softmmu.mak b/default-configs/devices/riscv32-softmmu.mak index 94a236c9c2..d847bd5692 100644 --- a/default-configs/devices/riscv32-softmmu.mak +++ b/default-configs/devices/riscv32-softmmu.mak @@ -3,6 +3,8 @@ # Uncomment the following lines to disable these optional devices: # #CONFIG_PCI_DEVICES=n +CONFIG_SEMIHOSTING=y +CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y # Boards: # diff --git a/default-configs/devices/riscv64-softmmu.mak b/default-configs/devices/riscv64-softmmu.mak index 76b6195648..d5eec75f05 100644 --- a/default-configs/devices/riscv64-softmmu.mak +++ b/default-configs/devices/riscv64-softmmu.mak @@ -3,6 +3,8 @@ # Uncomment the following lines to disable these optional devices: # #CONFIG_PCI_DEVICES=n +CONFIG_SEMIHOSTING=y +CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y # Boards: # diff --git a/default-configs/targets/riscv32-linux-user.mak b/default-configs/targets/riscv32-linux-user.mak index dfb259e8aa..6a9d1b1bc1 100644 --- a/default-configs/targets/riscv32-linux-user.mak +++ b/default-configs/targets/riscv32-linux-user.mak @@ -2,3 +2,4 @@ TARGET_ARCH=riscv32 TARGET_BASE_ARCH=riscv TARGET_ABI_DIR=riscv TARGET_XML_FILES= gdb-xml/riscv-32bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-32bit-csr.xml gdb-xml/riscv-32bit-virtual.xml +CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y diff --git a/default-configs/targets/riscv64-linux-user.mak b/default-configs/targets/riscv64-linux-user.mak index b13895f3b0..0a92849a1b 100644 --- a/default-configs/targets/riscv64-linux-user.mak +++ b/default-configs/targets/riscv64-linux-user.mak @@ -2,3 +2,4 @@ TARGET_ARCH=riscv64 TARGET_BASE_ARCH=riscv TARGET_ABI_DIR=riscv TARGET_XML_FILES= gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-64bit-csr.xml gdb-xml/riscv-64bit-virtual.xml +CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y diff --git a/hw/semihosting/common-semi.c b/hw/semihosting/common-semi.c index c77fb21bec..8675934a71 100644 --- a/hw/semihosting/common-semi.c +++ b/hw/semihosting/common-semi.c @@ -1,6 +1,6 @@ /* * Semihosting support for systems modeled on the Arm "Angel" - * semihosting syscalls design. + * semihosting syscalls design. This includes Arm and RISC-V processors * * Copyright (c) 2005, 2007 CodeSourcery. * Copyright (c) 2019 Linaro @@ -25,6 +25,10 @@ * ARM Semihosting is documented in: * Semihosting for AArch32 and AArch64 Release 2.0 * https://static.docs.arm.com/100863/0200/semihosting.pdf + * + * RISC-V Semihosting is documented in: + * RISC-V Semihosting + * https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc */ #include "qemu/osdep.h" @@ -163,6 +167,30 @@ common_semi_sys_exit_extended(CPUState *cs, int nr) } #endif /* TARGET_ARM */ +#ifdef TARGET_RISCV +static inline target_ulong
