Moving the below instructions to decodetree specification :
neg[o][.] : XO-form
mod{sw, uw}, darn : X-form
The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured with the '-d in_asm,op' flag.
Signed-off-by: Chinmay Rath
---
target/ppc/helper.h| 4 +-
target/ppc/insn32.decode | 8
target/ppc/int_helper.c| 4 +-
target/ppc/translate.c | 56 --
target/ppc/translate/fixedpoint-impl.c.inc | 44 +
5 files changed, 56 insertions(+), 60 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 1fc8b7c5fd..09d0b0074b 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -71,8 +71,8 @@ DEF_HELPER_FLAGS_2(cmpeqb, TCG_CALL_NO_RWG_SE, i32, tl, tl)
DEF_HELPER_FLAGS_1(popcntw, TCG_CALL_NO_RWG_SE, tl, tl)
DEF_HELPER_FLAGS_2(bpermd, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_3(srad, tl, env, tl, tl)
-DEF_HELPER_FLAGS_0(darn32, TCG_CALL_NO_RWG, tl)
-DEF_HELPER_FLAGS_0(darn64, TCG_CALL_NO_RWG, tl)
+DEF_HELPER_FLAGS_0(DARN32, TCG_CALL_NO_RWG, tl)
+DEF_HELPER_FLAGS_0(DARN64, TCG_CALL_NO_RWG, tl)
#endif
DEF_HELPER_FLAGS_1(cntlsw32, TCG_CALL_NO_RWG_SE, i32, i32)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index bfccebd9a7..654f55471b 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -187,6 +187,9 @@
_ara
@X_a.. ra:3 .. . . .. . _a
+_tl rt l
+@X_tl .. rt:5 ... l:2 . .. . _tl
+
rt ra rb oe:bool rc:bool
@XO .. rt:5 ra:5 rb:5 oe:1 . rc:1
@@ -367,6 +370,11 @@ DIVWU 01 . . . . 111001011 . @XO
DIVWE 01 . . . . 110101011 . @XO
DIVWEU 01 . . . . 110001011 . @XO
+MODSW 01 . . . 111011 - @X
+MODUW 01 . . . 011011 - @X
+DARN01 . --- .. - 100011 - @X_tl
+NEG 01 . . - . 001101000 . @XO_ta
+
## Fixed-Point Logical Instructions
CFUGED 01 . . . 0011011100 - @X
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index dc1f72ff38..bc25d5b062 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -171,7 +171,7 @@ uint32_t helper_cmpeqb(target_ulong ra, target_ulong rb)
/*
* Return a random number.
*/
-uint64_t helper_darn32(void)
+uint64_t helper_DARN32(void)
{
Error *err = NULL;
uint32_t ret;
@@ -186,7 +186,7 @@ uint64_t helper_darn32(void)
return ret;
}
-uint64_t helper_darn64(void)
+uint64_t helper_DARN64(void)
{
Error *err = NULL;
uint64_t ret;
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 0a1d1d63b3..436fcfc645 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -1878,17 +1878,6 @@ static inline void gen_op_arith_modw(DisasContext *ctx,
TCGv ret, TCGv arg1,
}
}
-#define GEN_INT_ARITH_MODW(name, opc3, sign)\
-static void glue(gen_, name)(DisasContext *ctx) \
-{ \
-gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)],\
- cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
- sign);\
-}
-
-GEN_INT_ARITH_MODW(moduw, 0x08, 0);
-GEN_INT_ARITH_MODW(modsw, 0x18, 1);
-
#if defined(TARGET_PPC64)
static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1,
TCGv arg2, int sign)
@@ -2055,27 +2044,6 @@ static inline void gen_op_arith_subf(DisasContext *ctx,
TCGv ret, TCGv arg1,
}
}
-/* neg neg. nego nego. */
-static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
-{
-TCGv zero = tcg_constant_tl(0);
-gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
- zero, 0, 0, compute_ov, Rc(ctx->opcode));
-}
-
-static void gen_neg(DisasContext *ctx)
-{
-tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
-if (unlikely(Rc(ctx->opcode))) {
-gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
-}
-}
-
-static void gen_nego(DisasContext *ctx)
-{
-gen_op_arith_neg(ctx, 1);
-}
-
/***Integer logical***/
#define GEN_LOGICAL2(name, tcg_op, opc, type) \
static void glue(gen_, name)(DisasContext *ctx) \
@@ -2401,24 +2369,6 @@ static void gen_cnttzd(DisasContext *ctx)
gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
}
}
-
-/* darn */
-static void
