KVM requires the target cpu to be at least ARMv8 architecture
(support on ARMv7 has been dropped in commit 82bf7ae84ce:
"target/arm: Remove KVM support for 32-bit Arm hosts").
A KVM-only build won't be able to run TCG cpus, move the
v7A CPU definitions to cpu_tcg.c.
Reported-by: Peter Maydell
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/cpu.c | 327 ---
target/arm/cpu_tcg.c | 310
2 files changed, 310 insertions(+), 327 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 2d8312267f7..3f10614778b 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1906,323 +1906,6 @@ static ObjectClass *arm_cpu_class_by_name(const char
*cpu_model)
return oc;
}
-/* CPU models. These are not needed for the AArch64 linux-user build. */
-#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
-
-static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
-{ .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-{ .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-REGINFO_SENTINEL
-};
-
-static void cortex_a8_initfn(Object *obj)
-{
-ARMCPU *cpu = ARM_CPU(obj);
-
-cpu->dtb_compatible = "arm,cortex-a8";
-set_feature(>env, ARM_FEATURE_V7);
-set_feature(>env, ARM_FEATURE_NEON);
-set_feature(>env, ARM_FEATURE_THUMB2EE);
-set_feature(>env, ARM_FEATURE_DUMMY_C15_REGS);
-set_feature(>env, ARM_FEATURE_EL3);
-cpu->midr = 0x410fc080;
-cpu->reset_fpsid = 0x410330c0;
-cpu->isar.mvfr0 = 0x0222;
-cpu->isar.mvfr1 = 0x0001;
-cpu->ctr = 0x82048004;
-cpu->reset_sctlr = 0x00c50078;
-cpu->isar.id_pfr0 = 0x1031;
-cpu->isar.id_pfr1 = 0x11;
-cpu->isar.id_dfr0 = 0x400;
-cpu->id_afr0 = 0;
-cpu->isar.id_mmfr0 = 0x3113;
-cpu->isar.id_mmfr1 = 0x2000;
-cpu->isar.id_mmfr2 = 0x01202000;
-cpu->isar.id_mmfr3 = 0x11;
-cpu->isar.id_isar0 = 0x0010;
-cpu->isar.id_isar1 = 0x12112111;
-cpu->isar.id_isar2 = 0x21232031;
-cpu->isar.id_isar3 = 0x2131;
-cpu->isar.id_isar4 = 0x0042;
-cpu->isar.dbgdidr = 0x15141000;
-cpu->clidr = (1 << 27) | (2 << 24) | 3;
-cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
-cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
-cpu->ccsidr[2] = 0xf000; /* No L2 icache. */
-cpu->reset_auxcr = 2;
-define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
-}
-
-static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
-/*
- * power_control should be set to maximum latency. Again,
- * default to 0 and set by private hook
- */
-{ .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
- .access = PL1_RW, .resetvalue = 0,
- .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
-{ .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
- .access = PL1_RW, .resetvalue = 0,
- .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
-{ .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 =
2,
- .access = PL1_RW, .resetvalue = 0,
- .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
-{ .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
- .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
-/* TLB lockdown control */
-{ .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
- .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
-{ .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
- .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
-{ .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
- .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
-{ .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
- .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
-{ .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
- .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
-REGINFO_SENTINEL
-};
-
-static void cortex_a9_initfn(Object *obj)
-{
-ARMCPU *cpu = ARM_CPU(obj);
-
-cpu->dtb_compatible = "arm,cortex-a9";
-set_feature(>env, ARM_FEATURE_V7);
-set_feature(>env, ARM_FEATURE_NEON);
-set_feature(>env, ARM_FEATURE_THUMB2EE);
-set_feature(>env, ARM_FEATURE_EL3);
-/*
- * Note that A9 supports the MP extensions even for
- * A9UP and single-core A9MP (which are both different
- * and valid configurations; we don't model A9UP).
- */
-set_feature(>env, ARM_FEATURE_V7MP);
-set_feature(>env, ARM_FEATURE_CBAR);
-cpu->midr = 0x410fc090;
-cpu->reset_fpsid = 0x41033090;
-cpu->isar.mvfr0 = 0x0222;
-cpu->isar.mvfr1 =
