Moving the below instructions to decodetree specification :
andi[s]., {ori, xori}[s]: D-form
{and, andc, nand, or, orc, nor, xor, eqv}[.],
exts{b, h, w}[.], cnt{l, t}z{w, d}[.],
popcnt{b, w, d}, prty{w, d}, cmp, bpermd : X-form
With this patch, all the fixed-point logical instructions have been
moved to decodetree.
The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured with the '-d in_asm,op' flag.
Signed-off-by: Chinmay Rath
---
target/ppc/helper.h| 8 +-
target/ppc/insn32.decode | 38 +++
target/ppc/int_helper.c| 10 +-
target/ppc/translate.c | 359 -
target/ppc/translate/fixedpoint-impl.c.inc | 269 +++
5 files changed, 316 insertions(+), 368 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 05f7ab5f6e..b53abd853a 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -58,8 +58,8 @@ DEF_HELPER_4(DIVDE, i64, env, i64, i64, i32)
DEF_HELPER_4(DIVWEU, tl, env, tl, tl, i32)
DEF_HELPER_4(DIVWE, tl, env, tl, tl, i32)
-DEF_HELPER_FLAGS_1(popcntb, TCG_CALL_NO_RWG_SE, tl, tl)
-DEF_HELPER_FLAGS_2(cmpb, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_1(POPCNTB, TCG_CALL_NO_RWG_SE, tl, tl)
+DEF_HELPER_FLAGS_2(CMPB, TCG_CALL_NO_RWG_SE, tl, tl, tl)
DEF_HELPER_3(sraw, tl, env, tl, tl)
DEF_HELPER_FLAGS_2(CFUGED, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(PDEPD, TCG_CALL_NO_RWG_SE, i64, i64, i64)
@@ -68,8 +68,8 @@ DEF_HELPER_FLAGS_1(CDTBCD, TCG_CALL_NO_RWG_SE, tl, tl)
DEF_HELPER_FLAGS_1(CBCDTD, TCG_CALL_NO_RWG_SE, tl, tl)
#if defined(TARGET_PPC64)
DEF_HELPER_FLAGS_2(CMPEQB, TCG_CALL_NO_RWG_SE, i32, tl, tl)
-DEF_HELPER_FLAGS_1(popcntw, TCG_CALL_NO_RWG_SE, tl, tl)
-DEF_HELPER_FLAGS_2(bpermd, TCG_CALL_NO_RWG_SE, i64, i64, i64)
+DEF_HELPER_FLAGS_1(POPCNTW, TCG_CALL_NO_RWG_SE, tl, tl)
+DEF_HELPER_FLAGS_2(BPERMD, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_3(srad, tl, env, tl, tl)
DEF_HELPER_FLAGS_0(DARN32, TCG_CALL_NO_RWG, tl)
DEF_HELPER_FLAGS_0(DARN64, TCG_CALL_NO_RWG, tl)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 80a7bb1872..3175810190 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -29,6 +29,9 @@
rt ra si:int64_t
@D .. rt:5 ra:5 si:s16
+_ui rt ra ui:uint64_t
+@D_ui .. rt:5 ra:5 ui:16 _ui
+
_bf bf l:bool ra imm
@D_bfs .. bf:3 . l:1 ra:5 imm:s16 _bf
@D_bfu .. bf:3 . l:1 ra:5 imm:16 _bf
@@ -96,6 +99,9 @@
_sa rs ra
@X_sa .. rs:5 ra:5 . .. . _sa
+_sa_rcrs ra rc
+@X_sa_rc.. rs:5 ra:5 . .. rc:1 _sa_rc
+
%x_frtp 22:4 !function=times_2
%x_frap 17:4 !function=times_2
%x_frbp 12:4 !function=times_2
@@ -410,6 +416,38 @@ MODUD 01 . . . 011001 - @X
## Fixed-Point Logical Instructions
+ANDI_ 011100 . . @D_ui
+ANDIS_ 011101 . . @D_ui
+ORI 011000 . . @D_ui
+ORIS011001 . . @D_ui
+XORI011010 . . @D_ui
+XORIS 011011 . . @D_ui
+
+AND 01 . . . 011100 . @X_rc
+ANDC01 . . . 00 . @X_rc
+NAND01 . . . 0111011100 . @X_rc
+OR 01 . . . 011000 . @X_rc
+ORC 01 . . . 0110011100 . @X_rc
+NOR 01 . . . 000100 . @X_rc
+XOR 01 . . . 010000 . @X_rc
+EQV 01 . . . 0100011100 . @X_rc
+CMPB01 . . . 011100 . @X_rc
+
+EXTSB 01 . . - 1110111010 . @X_sa_rc
+EXTSH 01 . . - 1110011010 . @X_sa_rc
+EXTSW 01 . . - 011010 . @X_sa_rc
+CNTLZW 01 . . - 011010 . @X_sa_rc
+CNTTZW 01 . . - 111010 . @X_sa_rc
+CNTLZD 01 . . - 111010 . @X_sa_rc
+CNTTZD 01 . . - 1000111010 . @X_sa_rc
+POPCNTB 01 . . - 000010 . @X_sa_rc
+
+POPCNTW 01 . . - 010010 - @X_sa
+POPCNTD 01 . . - 011010 - @X_sa
+PRTYW 01 . . - 0010011010 - @X_sa
+PRTYD 01 . . - 0010111010 - @X_sa
+
+BPERMD 01 . . . 001100 -
