On 2/22/2023 2:37 PM, Zhao Liu wrote:
Hi Xiaoyao,
Thanks, I've spent some time thinking about it here.
On Mon, Feb 20, 2023 at 02:59:20PM +0800, Xiaoyao Li wrote:
Date: Mon, 20 Feb 2023 14:59:20 +0800
From: Xiaoyao Li
Subject: Re: [PATCH RESEND 04/18] i386/cpu: Fix number of addressable IDs
Hi Xiaoyao,
Thanks, I've spent some time thinking about it here.
On Mon, Feb 20, 2023 at 02:59:20PM +0800, Xiaoyao Li wrote:
> Date: Mon, 20 Feb 2023 14:59:20 +0800
> From: Xiaoyao Li
> Subject: Re: [PATCH RESEND 04/18] i386/cpu: Fix number of addressable IDs
> in CPUID.04H
>
&
On 2/13/2023 5:36 PM, Zhao Liu wrote:
For i-cache and d-cache, the maximum IDs for CPUs sharing cache (
CPUID.04H.00H:EAX[bits 25:14] and CPUID.04H.01H:EAX[bits 25:14]) are
both 0, and this means i-cache and d-cache are shared in the SMT level.
This is correct if there's single thread per core,
On Wed, Feb 15, 2023 at 06:11:23PM +0800, wangyanan (Y) wrote:
> Date: Wed, 15 Feb 2023 18:11:23 +0800
> From: "wangyanan (Y)"
> Subject: Re: [PATCH RESEND 04/18] i386/cpu: Fix number of addressable IDs
> in CPUID.04H
>
> Hi Zhao,
>
> 在 2023/2/13 17:3
Hi Zhao,
在 2023/2/13 17:36, Zhao Liu 写道:
From: Zhao Liu
For i-cache and d-cache, the maximum IDs for CPUs sharing cache (
CPUID.04H.00H:EAX[bits 25:14] and CPUID.04H.01H:EAX[bits 25:14]) are
both 0, and this means i-cache and d-cache are shared in the SMT level.
This is correct if there's
From: Zhao Liu
For i-cache and d-cache, the maximum IDs for CPUs sharing cache (
CPUID.04H.00H:EAX[bits 25:14] and CPUID.04H.01H:EAX[bits 25:14]) are
both 0, and this means i-cache and d-cache are shared in the SMT level.
This is correct if there's single thread per core, but is wrong for the
