Re: [PATCH v1 4/5] target/riscv: progressively load the instruction during decode

On 2/7/20 7:01 AM, Alex Bennée wrote: > The plugin system would throw up a harmless warning when it detected > that a disassembly of an instruction didn't use all it's bytes. Fix > the riscv decoder to only load the instruction bytes it needs as it > needs them. > > This drops opcode from the ctx

Re: [PATCH v1 4/5] target/riscv: progressively load the instruction during decode

Robert Foley writes: > Hi, > On Fri, 7 Feb 2020 at 10:01, Alex Bennée wrote: >> -static void decode_RV32_64C0(DisasContext *ctx) >> +static void decode_RV32_64C0(DisasContext *ctx, uint16_t opcode) >> { >> -uint8_t funct3 = extract32(ctx->opcode, 13, 3); >> -uint8_t rd_rs2 =

Re: [PATCH v1 4/5] target/riscv: progressively load the instruction during decode

Hi, On Fri, 7 Feb 2020 at 10:01, Alex Bennée wrote: > -static void decode_RV32_64C0(DisasContext *ctx) > +static void decode_RV32_64C0(DisasContext *ctx, uint16_t opcode) > { > -uint8_t funct3 = extract32(ctx->opcode, 13, 3); > -uint8_t rd_rs2 = GET_C_RS2S(ctx->opcode); > -uint8_t

[PATCH v1 4/5] target/riscv: progressively load the instruction during decode

The plugin system would throw up a harmless warning when it detected that a disassembly of an instruction didn't use all it's bytes. Fix the riscv decoder to only load the instruction bytes it needs as it needs them. This drops opcode from the ctx in favour if passing the appropriately sized