Re: [PATCH v10 4/5] target/riscv: smstateen check for fcsr

2022-10-10 Thread weiwei
On 2022/10/7 01:06, mchit...@ventanamicro.com wrote: On Tue, 2022-10-04 at 21:23 +0800, weiwei wrote: On 2022/10/4 14:51, mchit...@ventanamicro.com wrote: On Mon, 2022-10-03 at 21:02 +0800, weiwei wrote: On 2022/10/3 19:47, Mayuresh Chitale wrote: If smstateen is implemented and

Re: [PATCH v10 4/5] target/riscv: smstateen check for fcsr

2022-10-06 Thread mchitale
On Tue, 2022-10-04 at 21:23 +0800, weiwei wrote: > > > > > On 2022/10/4 14:51, > mchit...@ventanamicro.com wrote: > > > > > > On Mon, 2022-10-03 at 21:02 +0800, weiwei wrote: > > > > > On 2022/10/3 19:47, Mayuresh Chitale wrote: > > >

Re: [PATCH v10 4/5] target/riscv: smstateen check for fcsr

2022-10-04 Thread weiwei
On 2022/10/4 14:51, mchit...@ventanamicro.com wrote: On Mon, 2022-10-03 at 21:02 +0800, weiwei wrote: On 2022/10/3 19:47, Mayuresh Chitale wrote: If smstateen is implemented and sstateen0.fcsr is clear then the floating point operations must return illegal instruction exception or virtual

Re: [PATCH v10 4/5] target/riscv: smstateen check for fcsr

2022-10-04 Thread mchitale
On Mon, 2022-10-03 at 21:02 +0800, weiwei wrote: > On 2022/10/3 19:47, Mayuresh Chitale wrote: > > If smstateen is implemented and sstateen0.fcsr is clear then the > > floating point > > operations must return illegal instruction exception or virtual > > instruction > > trap, if relevant. > > > >

Re: [PATCH v10 4/5] target/riscv: smstateen check for fcsr

2022-10-03 Thread weiwei
On 2022/10/3 19:47, Mayuresh Chitale wrote: If smstateen is implemented and sstateen0.fcsr is clear then the floating point operations must return illegal instruction exception or virtual instruction trap, if relevant. Signed-off-by: Mayuresh Chitale --- target/riscv/csr.c

[PATCH v10 4/5] target/riscv: smstateen check for fcsr

2022-10-03 Thread Mayuresh Chitale
If smstateen is implemented and sstateen0.fcsr is clear then the floating point operations must return illegal instruction exception or virtual instruction trap, if relevant. Signed-off-by: Mayuresh Chitale --- target/riscv/csr.c| 23