Implements FCVTLT, FCVTX, FCVTNT, FCVTXNT
Signed-off-by: Stephen Long
---
Fixed a compilation error and collapsed the translation functions with a
macro.
> Ignore my previous patchset. I missed the insn FCVTX and I ended up
> squashing those commits into this one. At the moment, I'm working on a
> patch for the SVE2 bitwise shift by imm insns.
target/arm/helper-sve.h| 16 +++
target/arm/sve.decode | 8 ++
target/arm/sve_helper.c| 59 ++
target/arm/translate-sve.c | 18
4 files changed, 101 insertions(+)
diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h
index 0a62eef94e..7c734334b2 100644
--- a/target/arm/helper-sve.h
+++ b/target/arm/helper-sve.h
@@ -2731,3 +2731,19 @@ DEF_HELPER_FLAGS_5(sve2_sqrdcmlah_idx_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve2_sqrdcmlah_idx_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_5(sve2_fcvtxnt, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,
i32)
+
+DEF_HELPER_FLAGS_5(sve2_fcvtnt_sh, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(sve2_fcvtnt_ds, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_5(sve2_fcvtlt_hs, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(sve2_fcvtlt_sd, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_5(do_fcvtx, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(sve2_fcvtx_ds, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, i32)
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index 3cf824bac5..bc48094ed8 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -1568,3 +1568,11 @@ SM4E01000101 00 10001 1 11100 0 . .
@rdn_rm_e0
# SVE2 crypto constructive binary operations
SM4EKEY 01000101 00 1 . 0 0 . . @rd_rn_rm_e0
RAX101000101 00 1 . 0 1 . . @rd_rn_rm_e0
+
+### SVE2 floating-point convert precision
+FCVTXNT 01100100 00 0010 10 101 ... . . @rd_pg_rn_e0
+FCVTNT_sh 01100100 10 0010 00 101 ... . . @rd_pg_rn_e0
+FCVTLT_hs 01100100 10 0010 01 101 ... . . @rd_pg_rn_e0
+FCVTNT_ds 01100100 11 0010 10 101 ... . . @rd_pg_rn_e0
+FCVTLT_sd 01100100 11 0010 11 101 ... . . @rd_pg_rn_e0
+FCVTX_ds01100101 00 0010 10 101 ... . . @rd_pg_rn_e0
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index aa94df302a..cb56148cdc 100644
--- a/target/arm/sve_helper.c
+++ b/target/arm/sve_helper.c
@@ -4624,6 +4624,8 @@ DO_ZPZ_FP(sve_ucvt_dh, uint64_t, , uint64_to_float16)
DO_ZPZ_FP(sve_ucvt_ds, uint64_t, , uint64_to_float32)
DO_ZPZ_FP(sve_ucvt_dd, uint64_t, , uint64_to_float64)
+DO_ZPZ_FP(do_fcvtx, uint64_t, , float64_to_float32)
+
#undef DO_ZPZ_FP
static void do_fmla_zpzzz_h(void *vd, void *vn, void *vm, void *va, void *vg,
@@ -7622,3 +7624,60 @@ void HELPER(fmmla_d)(void *vd, void *va, void *vn, void
*vm,
d[3] = float64_add(a[3], float64_add(p0, p1, status), status);
}
}
+
+#define DO_FCVTNT(NAME, TYPEW, TYPEN, HW, HN, OP) \
+void HELPER(NAME)(void *vd, void *vn, void *vg, void *status, uint32_t desc) \
+{ \
+intptr_t i = simd_oprsz(desc);\
+uint64_t *g = vg; \
+do { \
+uint64_t pg = g[(i - 1) >> 6];\
+do { \
+i -= sizeof(TYPEW); \
+if (likely((pg >> (i & 63)) & 1)) { \
+TYPEW nn = *(TYPEW *)(vn + HW(i));\
+*(TYPEN *)(vd + HN(i + sizeof(TYPEN))) = OP(nn, status); \
+} \
+} while (i & 63); \
+} while (i != 0); \
+}
+
+DO_FCVTNT(sve2_fcvtnt_sh, uint32_t, uint16_t, H1_4, H1_2, sve_f32_to_f16)
+DO_FCVTNT(sve2_fcvtnt_ds, uint64_t, uint32_t, H1_4, H1_2, float64_to_float32)
+
+void HELPER(sve2_fcvtxnt)(void *vd, void *vn, void *vg,
+ void *status, uint32_t desc)
+{
+set_float_rounding_mode(float_round_to_odd, status);
+HELPER(sve2_fcvtnt_ds)(vd, vn, vg, status, desc);
+}
+
+#define DO_FCVTLT(NAME, TYPEW, TYPEN, HW, HN, OP) \
