Given that the 128-bit version of the riscv spec adds new instructions, and that some instructions that were previously only available in 64-bit mode are now available for both 64-bit and 128-bit, we added new macros to check for the processor mode during translation.
Signed-off-by: Frédéric Pétrot <frederic.pet...@univ-grenoble-alpes.fr> Co-authored-by: Fabien Portas <fabien.por...@grenoble-inp.org> --- target/riscv/translate.c | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 3c929ce960..96a1e40606 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -357,11 +357,29 @@ EX_SH(12) } while (0) #define REQUIRE_64BIT(ctx) do { \ - if (is_32bit(ctx)) { \ + if (!is_64bit(ctx)) { \ return false; \ } \ } while (0) +#define REQUIRE_128BIT(ctx) do { \ + if (!is_128bit(ctx)) { \ + return false; \ + } \ +} while (0) + +#define REQUIRE_32_OR_64BIT(ctx) do { \ + if (is_128bit(ctx)) { \ + return false; \ + } \ +} while (0) + +#define REQUIRE_64_OR_128BIT(ctx) do { \ + if (is_32bit(ctx)) { \ + return false; \ + } \ +} while (0) + static int ex_rvc_register(DisasContext *ctx, int reg) { return 8 + reg; -- 2.33.0