Re: [PATCH v2 15/28] hw/intc/armv7m_nvic: Update FPDSCR masking for v8.1M

2020-12-01 Thread Richard Henderson
On 11/19/20 3:56 PM, Peter Maydell wrote: > The FPDSCR register has a similar layout to the FPSCR. In v8.1M it > gains new fields FZ16 (if half-precision floating point is supported) > and LTPSIZE (always reads as 4). Update the reset value and the code > that handles writes to this register

[PATCH v2 15/28] hw/intc/armv7m_nvic: Update FPDSCR masking for v8.1M

2020-11-19 Thread Peter Maydell
The FPDSCR register has a similar layout to the FPSCR. In v8.1M it gains new fields FZ16 (if half-precision floating point is supported) and LTPSIZE (always reads as 4). Update the reset value and the code that handles writes to this register accordingly. Signed-off-by: Peter Maydell ---