Re: [PATCH v2 2/5] target/arm: make ARMCPU.clidr 64-bit

2020-12-15 Thread Laurent Desnogues 
On Tue, Dec 15, 2020 at 12:52 PM Leif Lindholm  wrote:
>
> The AArch64 view of CLIDR_EL1 extends the ICB field to include also bit
> 32, as well as adding a Ttype field when FEAT_MTE is implemented.
> Extend the clidr field to be able to hold this context.
>
> Signed-off-by: Leif Lindholm 

Reviewed-by: Laurent Desnogues 

Thanks,

Laurent

> ---
>  target/arm/cpu.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index 5e3cf77ec7..fadd1a47df 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -938,7 +938,7 @@ struct ARMCPU {
>  uint32_t id_afr0;
>  uint64_t id_aa64afr0;
>  uint64_t id_aa64afr1;
> -uint32_t clidr;
> +uint64_t clidr;
>  uint64_t mp_affinity; /* MP ID without feature bits */
>  /* The elements of this array are the CCSIDR values for each cache,
>   * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc.
> --
> 2.20.1
>
>

[PATCH v2 2/5] target/arm: make ARMCPU.clidr 64-bit

2020-12-15 Thread Leif Lindholm 
The AArch64 view of CLIDR_EL1 extends the ICB field to include also bit
32, as well as adding a Ttype field when FEAT_MTE is implemented.
Extend the clidr field to be able to hold this context.

Signed-off-by: Leif Lindholm 
---
 target/arm/cpu.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 5e3cf77ec7..fadd1a47df 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -938,7 +938,7 @@ struct ARMCPU {
 uint32_t id_afr0;
 uint64_t id_aa64afr0;
 uint64_t id_aa64afr1;
-uint32_t clidr;
+uint64_t clidr;
 uint64_t mp_affinity; /* MP ID without feature bits */
 /* The elements of this array are the CCSIDR values for each cache,
  * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc.
-- 
2.20.1