Re: [PATCH v2 26/28] hw/intc/armv7m_nvic: Implement read/write for RAS register block

2020-12-01 Thread Richard Henderson
On 11/19/20 3:56 PM, Peter Maydell wrote: > The RAS feature has a block of memory-mapped registers at offset > 0x5000 within the PPB. For a "minimal RAS" implementation we provide > no error records and so the only registers that exist in the block > are ERRIIDR and ERRDEVID. > > The "RAZ/WI for

[PATCH v2 26/28] hw/intc/armv7m_nvic: Implement read/write for RAS register block

2020-11-19 Thread Peter Maydell
The RAS feature has a block of memory-mapped registers at offset 0x5000 within the PPB. For a "minimal RAS" implementation we provide no error records and so the only registers that exist in the block are ERRIIDR and ERRDEVID. The "RAZ/WI for privileged, BusFault for nonprivileged" behaviour of