Re: [PATCH v2 41/71] target/arm: Add infrastructure for disas_sme

2022-06-10 Thread Peter Maydell 
On Thu, 9 Jun 2022 at 23:58, Richard Henderson
 wrote:
>
> On 6/9/22 08:35, Peter Maydell wrote:
> >> +if (!disas_sme(s, insn)) {
> >> +unallocated_encoding(s);
> >> +}
> >> +break;
> >
> > I still think we should check bit 31 here.
>
> We don't do anything similar over in a32, where we've done the full 
> conversion:
>
>  if (disas_a32_uncond(s, insn) ||
>
>  disas_vfp_uncond(s, insn) ||
>
>  disas_neon_dp(s, insn) ||
>
>  disas_neon_ls(s, insn) ||
>
>  disas_neon_shared(s, insn)) {
>
>  return;
>
>  }

The difference there is that we've basically completed the decodetree
conversion. Here we're putting one decodetree disas call inside a
legacy decode, so we should put it at the right point in the
legacy structure, I think.

> and there's nothing else within major opcode 0 to conflict.

Yet :-)

-- PMM

Re: [PATCH v2 41/71] target/arm: Add infrastructure for disas_sme

2022-06-09 Thread Richard Henderson 

On 6/9/22 08:35, Peter Maydell wrote:

+if (!disas_sme(s, insn)) {
+unallocated_encoding(s);
+}
+break;


I still think we should check bit 31 here.


We don't do anything similar over in a32, where we've done the full conversion:

if (disas_a32_uncond(s, insn) ||

disas_vfp_uncond(s, insn) ||

disas_neon_dp(s, insn) ||

disas_neon_ls(s, insn) ||

disas_neon_shared(s, insn)) {

return;

}


and there's nothing else within major opcode 0 to conflict.

But if you insist, ok.


r~

Re: [PATCH v2 41/71] target/arm: Add infrastructure for disas_sme

2022-06-09 Thread Peter Maydell 
On Tue, 7 Jun 2022 at 21:36, Richard Henderson
 wrote:
>
> This includes the build rules for the decoder, and the
> new file for translation, but excludes any instructions.
>
> Signed-off-by: Richard Henderson 
> ---
>  target/arm/translate-a64.h |  1 +
>  target/arm/translate-a64.c |  7 ++-
>  target/arm/translate-sme.c | 35 +++
>  target/arm/meson.build |  2 ++
>  target/arm/sme.decode  | 20 
>  5 files changed, 64 insertions(+), 1 deletion(-)
>  create mode 100644 target/arm/translate-sme.c
>  create mode 100644 target/arm/sme.decode
>
> diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h
> index f0970c6b8c..789b6e8e78 100644
> --- a/target/arm/translate-a64.h
> +++ b/target/arm/translate-a64.h
> @@ -146,6 +146,7 @@ static inline int pred_gvec_reg_size(DisasContext *s)
>  }
>
>  bool disas_sve(DisasContext *, uint32_t);
> +bool disas_sme(DisasContext *, uint32_t);
>
>  void gen_gvec_rax1(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
> uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
> diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
> index b1d2840819..8a38fbc33b 100644
> --- a/target/arm/translate-a64.c
> +++ b/target/arm/translate-a64.c
> @@ -14814,7 +14814,12 @@ static void 
> aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
>  }
>
>  switch (extract32(insn, 25, 4)) {
> -case 0x0: case 0x1: case 0x3: /* UNALLOCATED */
> +case 0x0:
> +if (!disas_sme(s, insn)) {
> +unallocated_encoding(s);
> +}
> +break;

I still think we should check bit 31 here.


Otherwise
Reviewed-by: Peter Maydell 

thanks
-- PMM

[PATCH v2 41/71] target/arm: Add infrastructure for disas_sme

2022-06-07 Thread Richard Henderson 
This includes the build rules for the decoder, and the
new file for translation, but excludes any instructions.

Signed-off-by: Richard Henderson 
---
 target/arm/translate-a64.h |  1 +
 target/arm/translate-a64.c |  7 ++-
 target/arm/translate-sme.c | 35 +++
 target/arm/meson.build |  2 ++
 target/arm/sme.decode  | 20 
 5 files changed, 64 insertions(+), 1 deletion(-)
 create mode 100644 target/arm/translate-sme.c
 create mode 100644 target/arm/sme.decode

diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h
index f0970c6b8c..789b6e8e78 100644
--- a/target/arm/translate-a64.h
+++ b/target/arm/translate-a64.h
@@ -146,6 +146,7 @@ static inline int pred_gvec_reg_size(DisasContext *s)
 }
 
 bool disas_sve(DisasContext *, uint32_t);
+bool disas_sme(DisasContext *, uint32_t);
 
 void gen_gvec_rax1(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index b1d2840819..8a38fbc33b 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -14814,7 +14814,12 @@ static void aarch64_tr_translate_insn(DisasContextBase 
*dcbase, CPUState *cpu)
 }
 
 switch (extract32(insn, 25, 4)) {
-case 0x0: case 0x1: case 0x3: /* UNALLOCATED */
+case 0x0:
+if (!disas_sme(s, insn)) {
+unallocated_encoding(s);
+}
+break;
+case 0x1: case 0x3: /* UNALLOCATED */
 unallocated_encoding(s);
 break;
 case 0x2:
diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c
new file mode 100644
index 00..786c93fb2d
--- /dev/null
+++ b/target/arm/translate-sme.c
@@ -0,0 +1,35 @@
+/*
+ * AArch64 SME translation
+ *
+ * Copyright (c) 2022 Linaro, Ltd
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see .
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "tcg/tcg-op.h"
+#include "tcg/tcg-op-gvec.h"
+#include "tcg/tcg-gvec-desc.h"
+#include "translate.h"
+#include "exec/helper-gen.h"
+#include "translate-a64.h"
+#include "fpu/softfloat.h"
+
+
+/*
+ * Include the generated decoder.
+ */
+
+#include "decode-sme.c.inc"
diff --git a/target/arm/meson.build b/target/arm/meson.build
index 02c91f72bb..c47d86c609 100644
--- a/target/arm/meson.build
+++ b/target/arm/meson.build
@@ -1,5 +1,6 @@
 gen = [
   decodetree.process('sve.decode', extra_args: '--decode=disas_sve'),
+  decodetree.process('sme.decode', extra_args: '--decode=disas_sme'),
   decodetree.process('neon-shared.decode', extra_args: 
'--decode=disas_neon_shared'),
   decodetree.process('neon-dp.decode', extra_args: '--decode=disas_neon_dp'),
   decodetree.process('neon-ls.decode', extra_args: '--decode=disas_neon_ls'),
@@ -50,6 +51,7 @@ arm_ss.add(when: 'TARGET_AARCH64', if_true: files(
   'sme_helper.c',
   'translate-a64.c',
   'translate-sve.c',
+  'translate-sme.c',
 ))
 
 arm_softmmu_ss = ss.source_set()
diff --git a/target/arm/sme.decode b/target/arm/sme.decode
new file mode 100644
index 00..c25c031a71
--- /dev/null
+++ b/target/arm/sme.decode
@@ -0,0 +1,20 @@
+# AArch64 SME instruction descriptions
+#
+#  Copyright (c) 2022 Linaro, Ltd
+#
+# This library is free software; you can redistribute it and/or
+# modify it under the terms of the GNU Lesser General Public
+# License as published by the Free Software Foundation; either
+# version 2.1 of the License, or (at your option) any later version.
+#
+# This library is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+# Lesser General Public License for more details.
+#
+# You should have received a copy of the GNU Lesser General Public
+# License along with this library; if not, see .
+
+#
+# This file is processed by scripts/decodetree.py
+#
-- 
2.34.1