Re: [PATCH v3 4/4] target/arm: Implement Cortex-M55 model

[Richard Henderson]

On 12/10/20 2:14 PM, Peter Maydell wrote:
> Now that we have implemented all the features needed by the v8.1M
> architecture, we can add the model of the Cortex-M55.  This is the
> configuration without MVE support; we'll add MVE later.
> 
> Signed-off-by: Peter Maydell 
> ---
>  target/arm/cpu_tcg.c | 42 ++
>  1 file changed, 42 insertions(+)

Reviewed-by: Richard Henderson 

r~

[PATCH v3 4/4] target/arm: Implement Cortex-M55 model

[Peter Maydell]

Now that we have implemented all the features needed by the v8.1M
architecture, we can add the model of the Cortex-M55.  This is the
configuration without MVE support; we'll add MVE later.

Signed-off-by: Peter Maydell 
---
 target/arm/cpu_tcg.c | 42 ++
 1 file changed, 42 insertions(+)

diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index 0013e25412f..98544db2df3 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -401,6 +401,46 @@ static void cortex_m33_initfn(Object *obj)
 cpu->ctr = 0x8000c000;
 }
 
+static void cortex_m55_initfn(Object *obj)
+{
+ARMCPU *cpu = ARM_CPU(obj);
+
+set_feature(>env, ARM_FEATURE_V8);
+set_feature(>env, ARM_FEATURE_V8_1M);
+set_feature(>env, ARM_FEATURE_M);
+set_feature(>env, ARM_FEATURE_M_MAIN);
+set_feature(>env, ARM_FEATURE_M_SECURITY);
+set_feature(>env, ARM_FEATURE_THUMB_DSP);
+cpu->midr = 0x410fd221; /* r0p1 */
+cpu->revidr = 0;
+cpu->pmsav7_dregion = 16;
+cpu->sau_sregion = 8;
+/*
+ * These are the MVFR* values for the FPU, no MVE configuration;
+ * we will update them later when we implement MVE
+ */
+cpu->isar.mvfr0 = 0x10110221;
+cpu->isar.mvfr1 = 0x12100011;
+cpu->isar.mvfr2 = 0x0040;
+cpu->isar.id_pfr0 = 0x2030;
+cpu->isar.id_pfr1 = 0x0230;
+cpu->isar.id_dfr0 = 0x1020;
+cpu->id_afr0 = 0x;
+cpu->isar.id_mmfr0 = 0x00111040;
+cpu->isar.id_mmfr1 = 0x;
+cpu->isar.id_mmfr2 = 0x0100;
+cpu->isar.id_mmfr3 = 0x0011;
+cpu->isar.id_isar0 = 0x01103110;
+cpu->isar.id_isar1 = 0x02212000;
+cpu->isar.id_isar2 = 0x20232232;
+cpu->isar.id_isar3 = 0x0131;
+cpu->isar.id_isar4 = 0x01310132;
+cpu->isar.id_isar5 = 0x;
+cpu->isar.id_isar6 = 0x;
+cpu->clidr = 0x; /* caches not implemented */
+cpu->ctr = 0x8303c003;
+}
+
 static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
 /* Dummy the TCM region regs for the moment */
 { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
@@ -655,6 +695,8 @@ static const ARMCPUInfo arm_tcg_cpus[] = {
  .class_init = arm_v7m_class_init },
 { .name = "cortex-m33",  .initfn = cortex_m33_initfn,
  .class_init = arm_v7m_class_init },
+{ .name = "cortex-m55",  .initfn = cortex_m55_initfn,
+ .class_init = arm_v7m_class_init },
 { .name = "cortex-r5",   .initfn = cortex_r5_initfn },
 { .name = "cortex-r5f",  .initfn = cortex_r5f_initfn },
 { .name = "ti925t",  .initfn = ti925t_initfn },
-- 
2.20.1