Re: [PATCH v4 07/11] target/riscv: Support mcycle/minstret write operation

On Wed, Jan 12, 2022 at 3:58 AM Atish Patra wrote: > > On Sun, Jan 9, 2022 at 11:51 PM Bin Meng wrote: > > > > On Fri, Jan 7, 2022 at 10:14 AM Atish Patra wrote: > > > > > > From: Atish Patra > > > > > > mcycle/minstret are actually WARL registers and can be written with any > > > given value.

Re: [PATCH v4 07/11] target/riscv: Support mcycle/minstret write operation

On Sun, Jan 9, 2022 at 11:51 PM Bin Meng wrote: > > On Fri, Jan 7, 2022 at 10:14 AM Atish Patra wrote: > > > > From: Atish Patra > > > > mcycle/minstret are actually WARL registers and can be written with any > > given value. With SBI PMU extension, it will be used to store a initial > > value

Re: [PATCH v4 07/11] target/riscv: Support mcycle/minstret write operation

On Fri, Jan 7, 2022 at 10:14 AM Atish Patra wrote: > > From: Atish Patra > > mcycle/minstret are actually WARL registers and can be written with any > given value. With SBI PMU extension, it will be used to store a initial > value provided from supervisor OS. The Qemu also need prohibit the

[PATCH v4 07/11] target/riscv: Support mcycle/minstret write operation

From: Atish Patra mcycle/minstret are actually WARL registers and can be written with any given value. With SBI PMU extension, it will be used to store a initial value provided from supervisor OS. The Qemu also need prohibit the counter increment if mcountinhibit is set. Support mcycle/minstret