Consolidate most of the inputs and outputs of S1_ptw_translate
into a single structure. Plumb this through arm_ld*_ptw from
the controlling get_phys_addr_* routine.
Signed-off-by: Richard Henderson
---
v4: Replaces a different S1TranslateResult patch, and plumbs the
structure further out in the function call tree.
---
target/arm/ptw.c | 140 ++-
1 file changed, 79 insertions(+), 61 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index a977d09c6d..dee69ee743 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -14,9 +14,16 @@
#include "idau.h"
-static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
- MMUAccessType access_type, ARMMMUIdx mmu_idx,
- bool is_secure, bool s1_is_el0,
+typedef struct S1Translate {
+ARMMMUIdx in_mmu_idx;
+bool in_secure;
+bool out_secure;
+hwaddr out_phys;
+} S1Translate;
+
+static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
+ uint64_t address,
+ MMUAccessType access_type, bool s1_is_el0,
GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
__attribute__((nonnull));
@@ -211,28 +218,31 @@ static bool ptw_attrs_are_device(uint64_t hcr,
ARMCacheAttrs cacheattrs)
}
/* Translate a S1 pagetable walk through S2 if needed. */
-static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
- hwaddr addr, bool *is_secure_ptr,
- ARMMMUFaultInfo *fi)
+static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw,
+ hwaddr addr, ARMMMUFaultInfo *fi)
{
-bool is_secure = *is_secure_ptr;
+bool is_secure = ptw->in_secure;
ARMMMUIdx s2_mmu_idx = is_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2;
-if (arm_mmu_idx_is_stage1_of_2(mmu_idx) &&
+if (arm_mmu_idx_is_stage1_of_2(ptw->in_mmu_idx) &&
!regime_translation_disabled(env, s2_mmu_idx, is_secure)) {
GetPhysAddrResult s2 = {};
+S1Translate s2ptw = {
+.in_mmu_idx = s2_mmu_idx,
+.in_secure = is_secure,
+};
uint64_t hcr;
int ret;
-ret = get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, s2_mmu_idx,
- is_secure, false, , fi);
+ret = get_phys_addr_lpae(env, , addr, MMU_DATA_LOAD,
+ false, , fi);
if (ret) {
assert(fi->type != ARMFault_None);
fi->s2addr = addr;
fi->stage2 = true;
fi->s1ptw = true;
fi->s1ns = !is_secure;
-return ~0;
+return false;
}
hcr = arm_hcr_el2_eff_secstate(env, is_secure);
@@ -246,7 +256,7 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx
mmu_idx,
fi->stage2 = true;
fi->s1ptw = true;
fi->s1ns = !is_secure;
-return ~0;
+return false;
}
if (arm_is_secure_below_el3(env)) {
@@ -256,19 +266,21 @@ static hwaddr S1_ptw_translate(CPUARMState *env,
ARMMMUIdx mmu_idx,
} else {
is_secure = !(env->cp15.vtcr_el2 & VTCR_NSW);
}
-*is_secure_ptr = is_secure;
} else {
assert(!is_secure);
}
addr = s2.f.phys_addr;
}
-return addr;
+
+ptw->out_secure = is_secure;
+ptw->out_phys = addr;
+return true;
}
/* All loads done in the course of a page table walk go through here. */
-static uint32_t arm_ldl_ptw(CPUARMState *env, hwaddr addr, bool is_secure,
-ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi)
+static uint32_t arm_ldl_ptw(CPUARMState *env, S1Translate *ptw, hwaddr addr,
+ARMMMUFaultInfo *fi)
{
CPUState *cs = env_cpu(env);
MemTxAttrs attrs = {};
@@ -276,13 +288,13 @@ static uint32_t arm_ldl_ptw(CPUARMState *env, hwaddr
addr, bool is_secure,
AddressSpace *as;
uint32_t data;
-addr = S1_ptw_translate(env, mmu_idx, addr, _secure, fi);
-attrs.secure = is_secure;
-as = arm_addressspace(cs, attrs);
-if (fi->s1ptw) {
+if (!S1_ptw_translate(env, ptw, addr, fi)) {
return 0;
}
-if (regime_translation_big_endian(env, mmu_idx)) {
+addr = ptw->out_phys;
+attrs.secure = ptw->out_secure;
+as = arm_addressspace(cs, attrs);
+if (regime_translation_big_endian(env, ptw->in_mmu_idx)) {
data = address_space_ldl_be(as, addr, attrs, );
} else {
data = address_space_ldl_le(as, addr, attrs, );
@@ -295,8 +307,8 @@ static uint32_t arm_ldl_ptw(CPUARMState *env, hwaddr addr,
bool is_secure,
return 0;
}
-static uint64_t arm_ldq_ptw(CPUARMState *env, hwaddr addr, bool is_secure,
-ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi)
+static
