Re: [PATCH v5 04/60] target/riscv: add vector configure instruction

2020-03-13 Thread Richard Henderson
On 3/12/20 7:58 AM, LIU Zhiwei wrote: > +static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl * a) > +{ > +TCGv s1, s2, dst; > +s2 = tcg_temp_new(); > +dst = tcg_temp_new(); > + > +/* Using x0 as the rs1 register specifier, encodes an infinite AVL */ > +if (a->rs1 == 0) { > +

Re: [PATCH v5 04/60] target/riscv: add vector configure instruction

2020-03-12 Thread Alistair Francis
On Thu, Mar 12, 2020 at 3:00 PM LIU Zhiwei wrote: > > > > On 2020/3/13 5:23, Alistair Francis wrote: > > On Thu, Mar 12, 2020 at 8:07 AM LIU Zhiwei wrote: > >> vsetvl and vsetvli are two configure instructions for vl, vtype. TB flags > >> should update after configure instructions. The (ill, lmul

Re: [PATCH v5 04/60] target/riscv: add vector configure instruction

2020-03-12 Thread LIU Zhiwei
On 2020/3/13 5:23, Alistair Francis wrote: On Thu, Mar 12, 2020 at 8:07 AM LIU Zhiwei wrote: vsetvl and vsetvli are two configure instructions for vl, vtype. TB flags should update after configure instructions. The (ill, lmul, sew ) of vtype and the bit of (VSTART == 0 && VL == VLMAX) will b

Re: [PATCH v5 04/60] target/riscv: add vector configure instruction

2020-03-12 Thread Alistair Francis
On Thu, Mar 12, 2020 at 8:07 AM LIU Zhiwei wrote: > > vsetvl and vsetvli are two configure instructions for vl, vtype. TB flags > should update after configure instructions. The (ill, lmul, sew ) of vtype > and the bit of (VSTART == 0 && VL == VLMAX) will be placed within tb_flags. > > Signed-off-

[PATCH v5 04/60] target/riscv: add vector configure instruction

2020-03-12 Thread LIU Zhiwei
vsetvl and vsetvli are two configure instructions for vl, vtype. TB flags should update after configure instructions. The (ill, lmul, sew ) of vtype and the bit of (VSTART == 0 && VL == VLMAX) will be placed within tb_flags. Signed-off-by: LIU Zhiwei --- target/riscv/Makefile.objs |