Re: [PATCH v8 07/12] target/riscv: Support mcycle/minstret write operation

On Sat, May 14, 2022 at 12:46 AM Frank Chang wrote: > > On Fri, May 13, 2022 at 11:58 PM Atish Kumar Patra > wrote: >> >> On Thu, May 12, 2022 at 11:29 PM Frank Chang wrote: >> > >> > On Thu, May 12, 2022 at 6:01 AM Atish Patra wrote: >> >> >> >> From: Atish Patra >> >> >> >> mcycle/minstret

Re: [PATCH v8 07/12] target/riscv: Support mcycle/minstret write operation

On Fri, May 13, 2022 at 11:58 PM Atish Kumar Patra wrote: > On Thu, May 12, 2022 at 11:29 PM Frank Chang > wrote: > > > > On Thu, May 12, 2022 at 6:01 AM Atish Patra wrote: > >> > >> From: Atish Patra > >> > >> mcycle/minstret are actually WARL registers and can be written with any > >> given

Re: [PATCH v8 07/12] target/riscv: Support mcycle/minstret write operation

On Thu, May 12, 2022 at 11:29 PM Frank Chang wrote: > > On Thu, May 12, 2022 at 6:01 AM Atish Patra wrote: >> >> From: Atish Patra >> >> mcycle/minstret are actually WARL registers and can be written with any >> given value. With SBI PMU extension, it will be used to store a initial >> value

Re: [PATCH v8 07/12] target/riscv: Support mcycle/minstret write operation

On Thu, May 12, 2022 at 6:01 AM Atish Patra wrote: > From: Atish Patra > > mcycle/minstret are actually WARL registers and can be written with any > given value. With SBI PMU extension, it will be used to store a initial > value provided from supervisor OS. The Qemu also need prohibit the

[PATCH v8 07/12] target/riscv: Support mcycle/minstret write operation

From: Atish Patra mcycle/minstret are actually WARL registers and can be written with any given value. With SBI PMU extension, it will be used to store a initial value provided from supervisor OS. The Qemu also need prohibit the counter increment if mcountinhibit is set. Support mcycle/minstret