On Fri, Oct 15, 2021 at 6:15 PM wrote:
>
> From: Frank Chang
>
> NaN-boxed the scalar floating-point register based on RVV 1.0's rules.
>
> Signed-off-by: Frank Chang
Acked-by: Alistair Francis
Alistair
> ---
> target/riscv/insn32.decode | 4 +--
> target/riscv/insn_trans/trans_rvv.c.inc | 38 -
> target/riscv/internals.h| 5
> 3 files changed, 21 insertions(+), 26 deletions(-)
>
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index e33ec82fdf8..ab5fdbf9be8 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -637,8 +637,8 @@ vid_v 010100 . 0 10001 010 . 1010111
> @r1_vm
> vmv_x_s 01 1 . 0 010 . 1010111 @r2rd
> vmv_s_x 01 1 0 . 110 . 1010111 @r2
> vext_x_v001100 1 . . 010 . 1010111 @r
> -vfmv_f_s001100 1 . 0 001 . 1010111 @r2rd
> -vfmv_s_f001101 1 0 . 101 . 1010111 @r2
> +vfmv_f_s01 1 . 0 001 . 1010111 @r2rd
> +vfmv_s_f01 1 0 . 101 . 1010111 @r2
> vslideup_vx 001110 . . . 100 . 1010111 @r_vm
> vslideup_vi 001110 . . . 011 . 1010111 @r_vm
> vslide1up_vx001110 . . . 110 . 1010111 @r_vm
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
> b/target/riscv/insn_trans/trans_rvv.c.inc
> index 1340ce56806..aec0316fba4 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -3046,14 +3046,19 @@ static bool trans_vmv_s_x(DisasContext *s,
> arg_vmv_s_x *a)
> /* Floating-Point Scalar Move Instructions */
> static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_f_s *a)
> {
> -if (!s->vill && has_ext(s, RVF) &&
> -(s->mstatus_fs != 0) && (s->sew != 0)) {
> -unsigned int len = 8 << s->sew;
> +if (require_rvv(s) &&
> +require_rvf(s) &&
> +vext_check_isa_ill(s)) {
> +unsigned int ofs = (8 << s->sew);
> +unsigned int len = 64 - ofs;
> +TCGv_i64 t_nan;
>
> vec_element_loadi(s, cpu_fpr[a->rd], a->rs2, 0, false);
> -if (len < 64) {
> -tcg_gen_ori_i64(cpu_fpr[a->rd], cpu_fpr[a->rd],
> -MAKE_64BIT_MASK(len, 64 - len));
> +/* NaN-box f[rd] as necessary for SEW */
> +if (len) {
> +t_nan = tcg_constant_i64(UINT64_MAX);
> +tcg_gen_deposit_i64(cpu_fpr[a->rd], cpu_fpr[a->rd],
> +t_nan, ofs, len);
> }
>
> mark_fs_dirty(s);
> @@ -3065,25 +3070,20 @@ static bool trans_vfmv_f_s(DisasContext *s,
> arg_vfmv_f_s *a)
> /* vfmv.s.f vd, rs1 # vd[0] = rs1 (vs2=0) */
> static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a)
> {
> -if (!s->vill && has_ext(s, RVF) && (s->sew != 0)) {
> -TCGv_i64 t1;
> +if (require_rvv(s) &&
> +require_rvf(s) &&
> +vext_check_isa_ill(s)) {
> /* The instructions ignore LMUL and vector register group. */
> -uint32_t vlmax = s->vlen >> 3;
> +TCGv_i64 t1;
> +TCGLabel *over = gen_new_label();
>
> /* if vl == 0, skip vector register write back */
> -TCGLabel *over = gen_new_label();
> tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
>
> -/* zeroed all elements */
> -tcg_gen_gvec_dup_imm(SEW64, vreg_ofs(s, a->rd), vlmax, vlmax, 0);
> -
> -/* NaN-box f[rs1] as necessary for SEW */
> +/* NaN-box f[rs1] */
> t1 = tcg_temp_new_i64();
> -if (s->sew == MO_64 && !has_ext(s, RVD)) {
> -tcg_gen_ori_i64(t1, cpu_fpr[a->rs1], MAKE_64BIT_MASK(32, 32));
> -} else {
> -tcg_gen_mov_i64(t1, cpu_fpr[a->rs1]);
> -}
> +do_nanbox(s, t1, cpu_fpr[a->rs1]);
> +
> vec_element_storei(s, a->rd, 0, t1);
> tcg_temp_free_i64(t1);
> mark_vs_dirty(s);
> diff --git a/target/riscv/internals.h b/target/riscv/internals.h
> index 81f5dfa477a..ac062dc0b4e 100644
> --- a/target/riscv/internals.h
> +++ b/target/riscv/internals.h
> @@ -32,11 +32,6 @@ target_ulong fclass_h(uint64_t frs1);
> target_ulong fclass_s(uint64_t frs1);
> target_ulong fclass_d(uint64_t frs1);
>
> -#define SEW8 0
> -#define SEW16 1
> -#define SEW32 2
> -#define SEW64 3
> -
> #ifndef CONFIG_USER_ONLY
> extern const VMStateDescription vmstate_riscv_cpu;
> #endif
> --
> 2.25.1
>
>
