Re: [PULL 00/21] target-arm queue

[Richard Henderson]

On 4/30/24 09:48, Peter Maydell wrote:

Here's another arm pullreq; nothing too exciting in here I think.

thanks
-- PMM

The following changes since commit 5fee33d97a7f2e95716417bd164f2f5264acd976:

   Merge tag 'samuel-thibault' ofhttps://people.debian.org/~sthibault/qemu  
into staging (2024-04-29 14:34:25 -0700)

are available in the Git repository at:

   https://git.linaro.org/people/pmaydell/qemu-arm.git  
tags/pull-target-arm-20240430

for you to fetch changes up to a0c325c4b05cf7815739d6a84e567b95c8c5be7e:

   tests/qtest : Add testcase for DM163 (2024-04-30 16:05:08 +0100)


target-arm queue:
  * hw/core/clock: allow clock_propagate on child clocks
  * hvf: arm: Remove unused PL1_WRITE_MASK define
  * target/arm: Restrict translation disabled alignment check to VMSA
  * docs/system/arm/emulation.rst: Add missing implemented features
  * target/arm: Enable FEAT_CSV2_3, FEAT_ETS2, FEAT_Spec_FPACC for 'max'
  * tests/avocado: update sunxi kernel from armbian to 6.6.16
  * target/arm: Make new CPUs default to 1GHz generic timer
  * hw/dmax/xlnx_dpdma: fix handling of address_extension descriptor fields
  * hw/char/stm32l4x5_usart: Fix memory corruption by adding correct class_size
  * hw/arm/npcm7xx: Store derivative OTP fuse key in little endian
  * hw/arm: Add DM163 display to B-L475E-IOT01A board


Applied, thanks.  Please update https://wiki.qemu.org/ChangeLog/9.1 as 
appropriate.


r~

[PULL 00/21] target-arm queue

[Peter Maydell]

Here's another arm pullreq; nothing too exciting in here I think.

thanks
-- PMM

The following changes since commit 5fee33d97a7f2e95716417bd164f2f5264acd976:

  Merge tag 'samuel-thibault' of https://people.debian.org/~sthibault/qemu into 
staging (2024-04-29 14:34:25 -0700)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git 
tags/pull-target-arm-20240430

for you to fetch changes up to a0c325c4b05cf7815739d6a84e567b95c8c5be7e:

  tests/qtest : Add testcase for DM163 (2024-04-30 16:05:08 +0100)


target-arm queue:
 * hw/core/clock: allow clock_propagate on child clocks
 * hvf: arm: Remove unused PL1_WRITE_MASK define
 * target/arm: Restrict translation disabled alignment check to VMSA
 * docs/system/arm/emulation.rst: Add missing implemented features
 * target/arm: Enable FEAT_CSV2_3, FEAT_ETS2, FEAT_Spec_FPACC for 'max'
 * tests/avocado: update sunxi kernel from armbian to 6.6.16
 * target/arm: Make new CPUs default to 1GHz generic timer
 * hw/dmax/xlnx_dpdma: fix handling of address_extension descriptor fields
 * hw/char/stm32l4x5_usart: Fix memory corruption by adding correct class_size
 * hw/arm/npcm7xx: Store derivative OTP fuse key in little endian
 * hw/arm: Add DM163 display to B-L475E-IOT01A board


Alexandra Diupina (1):
  hw/dmax/xlnx_dpdma: fix handling of address_extension descriptor fields

Inès Varhol (5):
  hw/display : Add device DM163
  hw/arm : Pass STM32L4x5 SYSCFG gpios to STM32L4x5 SoC
  hw/arm : Create Bl475eMachineState
  hw/arm : Connect DM163 to B-L475E-IOT01A
  tests/qtest : Add testcase for DM163

Peter Maydell (10):
  docs/system/arm/emulation.rst: Add missing implemented features
  target/arm: Enable FEAT_CSV2_3 for -cpu max
  target/arm: Enable FEAT_ETS2 for -cpu max
  target/arm: Implement ID_AA64MMFR3_EL1
  target/arm: Enable FEAT_Spec_FPACC for -cpu max
  tests/avocado: update sunxi kernel from armbian to 6.6.16
  target/arm: Refactor default generic timer frequency handling
  hw/arm/sbsa-ref: Force CPU generic timer to 62.5MHz
  hw/watchdog/sbsa_gwdt: Make watchdog timer frequency a QOM property
  target/arm: Default to 1GHz cntfrq for 'max' and new CPUs

Philippe Mathieu-Daudé (1):
  hw/arm/npcm7xx: Store derivative OTP fuse key in little endian

Raphael Poggi (1):
  hw/core/clock: allow clock_propagate on child clocks

Richard Henderson (1):
  target/arm: Restrict translation disabled alignment check to VMSA

Thomas Huth (1):
  hw/char/stm32l4x5_usart: Fix memory corruption by adding correct 
class_size

Zenghui Yu (1):
  hvf: arm: Remove PL1_WRITE_MASK

 docs/system/arm/b-l475e-iot01a.rst  |   3 +-
 docs/system/arm/emulation.rst   |  42 -
 include/hw/display/dm163.h  |  59 ++
 include/hw/watchdog/sbsa_gwdt.h |   3 +-
 target/arm/cpu.h|  28 +++
 target/arm/internals.h  |  15 +-
 hw/arm/b-l475e-iot01a.c | 105 +--
 hw/arm/npcm7xx.c|   3 +-
 hw/arm/sbsa-ref.c   |  16 ++
 hw/arm/stm32l4x5_soc.c  |   6 +-
 hw/char/stm32l4x5_usart.c   |   1 +
 hw/core/clock.c |   1 -
 hw/core/machine.c   |   4 +-
 hw/display/dm163.c  | 349 
 hw/dma/xlnx_dpdma.c |  20 +--
 hw/watchdog/sbsa_gwdt.c |  15 +-
 target/arm/cpu.c|  42 +++--
 target/arm/cpu64.c  |   2 +
 target/arm/helper.c |  22 +--
 target/arm/hvf/hvf.c|   3 +-
 target/arm/kvm.c|   2 +
 target/arm/tcg/cpu32.c  |   6 +-
 target/arm/tcg/cpu64.c  |  28 ++-
 target/arm/tcg/hflags.c |  12 +-
 tests/qtest/dm163-test.c| 194 
 tests/qtest/stm32l4x5_gpio-test.c   |  13 +-
 tests/qtest/stm32l4x5_syscfg-test.c |  17 +-
 hw/arm/Kconfig  |   1 +
 hw/display/Kconfig  |   3 +
 hw/display/meson.build  |   1 +
 hw/display/trace-events |  14 ++
 tests/avocado/boot_linux_console.py |  70 
 tests/avocado/replay_kernel.py  |   8 +-
 tests/qtest/meson.build |   2 +
 34 files changed, 987 insertions(+), 123 deletions(-)
 create mode 100644 include/hw/display/dm163.h
 create mode 100644 hw/display/dm163.c
 create mode 100644 tests/qtest/dm163-test.c

[PULL 00/21] target-arm queue

[Peter Maydell]

The following changes since commit 977542ded7e6b28d2bc077bcda24568c716e393c:

  Merge tag 'pull-testing-updates-120124-2' of https://gitlab.com/stsquad/qemu 
into staging (2024-01-12 14:02:53 +)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git 
tags/pull-target-arm-20240116

for you to fetch changes up to 7ec39730a9cc443c752d4cad2bf1c00467551ef5:

  load_elf: fix iterator's type for elf file processing (2024-01-15 17:14:22 
+)


target-arm queue:
 * docs/devel/docs: Document .hx file syntax
 * arm_pamax() no longer needs to do feature propagation
 * docs/system/arm/virt.rst: Improve 'highmem' option docs
 * STM32L4x5 Implement SYSCFG and EXTI devices
 * Nuvoton: Implement PCI Mailbox module
 * Nuvoton: Implement GMAC module
 * hw/timer: fix systick trace message
 * hw/arm/virt: Consolidate valid CPU types
 * load_elf: fix iterator's type for elf file processing


Anastasia Belova (1):
  load_elf: fix iterator's type for elf file processing

Gavin Shan (1):
  hw/arm/virt: Consolidate valid CPU types

Hao Wu (3):
  hw/misc: Add Nuvoton's PCI Mailbox Module
  hw/misc: Add qtest for NPCM7xx PCI Mailbox
  hw/arm: Add GMAC devices to NPCM7XX SoC

Inès Varhol (6):
  hw/misc: Implement STM32L4x5 EXTI
  hw/arm: Connect STM32L4x5 EXTI to STM32L4x5 SoC
  tests/qtest: Add STM32L4x5 EXTI QTest testcase
  hw/misc: Implement STM32L4x5 SYSCFG
  hw/arm: Connect STM32L4x5 SYSCFG to STM32L4x5 SoC
  tests/qtest: Add STM32L4x5 SYSCFG QTest testcase

Nabih Estefan Diaz (4):
  tests/qtest: Creating qtest for GMAC Module
  hw/net: GMAC Rx Implementation
  hw/net: GMAC Tx Implementation
  tests/qtest: Adding PCS Module test to GMAC Qtest

Peter Maydell (5):
  docs/devel/docs: Document .hx file syntax
  target/arm: arm_pamax() no longer needs to do feature propagation
  docs/system/arm/virt.rst: Improve 'highmem' option docs
  hw/arm: Add PCI mailbox module to Nuvoton SoC
  hw/net: Add NPCMXXX GMAC device

Samuel Tardieu (1):
  hw/timer: fix systick trace message

 MAINTAINERS |   1 +
 docs/devel/docs.rst |  60 +++
 docs/devel/index-build.rst  |   1 +
 docs/system/arm/b-l475e-iot01a.rst  |   7 +-
 docs/system/arm/nuvoton.rst |   2 +
 docs/system/arm/virt.rst|   8 +-
 include/hw/arm/npcm7xx.h|   4 +
 include/hw/arm/stm32l4x5_soc.h  |   5 +
 include/hw/elf_ops.h|   2 +-
 include/hw/misc/npcm7xx_pci_mbox.h  |  81 
 include/hw/misc/stm32l4x5_exti.h|  51 ++
 include/hw/misc/stm32l4x5_syscfg.h  |  54 +++
 include/hw/net/npcm_gmac.h  | 340 +
 hw/arm/npcm7xx.c|  53 +-
 hw/arm/stm32l4x5_soc.c  |  73 ++-
 hw/arm/virt.c   |   8 +-
 hw/misc/npcm7xx_pci_mbox.c  | 324 +
 hw/misc/stm32l4x5_exti.c| 290 +++
 hw/misc/stm32l4x5_syscfg.c  | 266 ++
 hw/net/npcm_gmac.c  | 939 
 target/arm/ptw.c|  14 +-
 tests/qtest/npcm7xx_pci_mbox-test.c | 238 +
 tests/qtest/npcm_gmac-test.c| 341 +
 tests/qtest/stm32l4x5_exti-test.c   | 524 
 tests/qtest/stm32l4x5_syscfg-test.c | 331 +
 hmp-commands-info.hx|  10 +-
 hmp-commands.hx |  10 +-
 hw/arm/Kconfig  |   2 +
 hw/misc/Kconfig |   6 +
 hw/misc/meson.build |   3 +
 hw/misc/trace-events|  16 +
 hw/net/meson.build  |   2 +-
 hw/net/trace-events |  19 +
 hw/timer/trace-events   |   2 +-
 qemu-img-cmds.hx|   2 +
 qemu-options.hx |   2 +
 tests/qtest/meson.build |   8 +
 37 files changed, 4066 insertions(+), 33 deletions(-)
 create mode 100644 docs/devel/docs.rst
 create mode 100644 include/hw/misc/npcm7xx_pci_mbox.h
 create mode 100644 include/hw/misc/stm32l4x5_exti.h
 create mode 100644 include/hw/misc/stm32l4x5_syscfg.h
 create mode 100644 include/hw/net/npcm_gmac.h
 create mode 100644 hw/misc/npcm7xx_pci_mbox.c
 create mode 100644 hw/misc/stm32l4x5_exti.c
 create mode 100644 hw/misc/stm32l4x5_syscfg.c
 create mode 100644 hw/net/npcm_gmac.c
 create mode 100644 tests/qtest/npcm7xx_pci_mbox-test.c
 create mode 100644 tests/qtest/npcm_gmac-test.c
 create mode 100644 tests/qtest/stm32l4x5_exti-test.c
 create mode 100644 tests/qtest/stm32l4x5_syscfg-test.c

Re: [PULL 00/21] target-arm queue

[Richard Henderson]

On 5/30/23 06:25, Peter Maydell wrote:

Hi; here's the latest batch of arm changes. The big thing
in here is the SMMUv3 changes to add stage-2 translation support.

thanks
-- PMM

The following changes since commit aa9bbd865502ed517624ab6fe7d4b5d89ca95e43:

   Merge tag 'pull-ppc-20230528' of https://gitlab.com/danielhb/qemu into 
staging (2023-05-29 14:31:52 -0700)

are available in the Git repository at:

   https://git.linaro.org/people/pmaydell/qemu-arm.git 
tags/pull-target-arm-20230530

for you to fetch changes up to b03d0d4f531a8b867e0aac1fab0b876903015680:

   docs: sbsa: correct graphics card name (2023-05-30 13:32:46 +0100)


target-arm queue:
  * fsl-imx6: Add SNVS support for i.MX6 boards
  * smmuv3: Add support for stage 2 translations
  * hw/dma/xilinx_axidma: Check DMASR.HALTED to prevent infinite loop
  * hw/arm/xlnx-zynqmp: fix unsigned error when checking the RPUs number
  * cleanups for recent Kconfig changes
  * target/arm: Explicitly select short-format FSR for M-profile
  * tests/qtest: Run arm-specific tests only if the required machine is 
available
  * hw/arm/sbsa-ref: add GIC node into DT
  * docs: sbsa: correct graphics card name
  * Update copyright dates to 2023


Printf failure on aarch64-macos and cross-mipsel:

https://gitlab.com/qemu-project/qemu/-/jobs/4374716505#L3662
https://gitlab.com/qemu-project/qemu/-/jobs/4374716612#L4963

../hw/arm/smmuv3.c:423:23: error: format specifies type 'unsigned long' but the argument 
has type 'uint64_t' (aka 'unsigned long long') [-Werror,-Wformat]

  cfg->s2cfg.vttb,  cfg->s2cfg.eff_ps);
  ^~~
/private/var/folders/76/zy5ktkns50v6gt5g8r0sf6scgn/T/cirrus-ci-build/include/qemu/log.h:54:30: 
note: expanded from macro 'qemu_log_mask'

qemu_log(FMT, ## __VA_ARGS__);  \
 ~~~ ^~~


r~

[PULL 00/21] target-arm queue

[Peter Maydell]

Hi; here's the latest batch of arm changes. The big thing
in here is the SMMUv3 changes to add stage-2 translation support.

thanks
-- PMM

The following changes since commit aa9bbd865502ed517624ab6fe7d4b5d89ca95e43:

  Merge tag 'pull-ppc-20230528' of https://gitlab.com/danielhb/qemu into 
staging (2023-05-29 14:31:52 -0700)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git 
tags/pull-target-arm-20230530

for you to fetch changes up to b03d0d4f531a8b867e0aac1fab0b876903015680:

  docs: sbsa: correct graphics card name (2023-05-30 13:32:46 +0100)


target-arm queue:
 * fsl-imx6: Add SNVS support for i.MX6 boards
 * smmuv3: Add support for stage 2 translations
 * hw/dma/xilinx_axidma: Check DMASR.HALTED to prevent infinite loop
 * hw/arm/xlnx-zynqmp: fix unsigned error when checking the RPUs number
 * cleanups for recent Kconfig changes
 * target/arm: Explicitly select short-format FSR for M-profile
 * tests/qtest: Run arm-specific tests only if the required machine is available
 * hw/arm/sbsa-ref: add GIC node into DT
 * docs: sbsa: correct graphics card name
 * Update copyright dates to 2023


Clément Chigot (1):
  hw/arm/xlnx-zynqmp: fix unsigned error when checking the RPUs number

Enze Li (1):
  Update copyright dates to 2023

Fabiano Rosas (3):
  target/arm: Explain why we need to select ARM_V7M
  arm/Kconfig: Keep Kconfig default entries in default.mak as documentation
  arm/Kconfig: Make TCG dependence explicit

Marcin Juszkiewicz (2):
  hw/arm/sbsa-ref: add GIC node into DT
  docs: sbsa: correct graphics card name

Mostafa Saleh (10):
  hw/arm/smmuv3: Add missing fields for IDR0
  hw/arm/smmuv3: Update translation config to hold stage-2
  hw/arm/smmuv3: Refactor stage-1 PTW
  hw/arm/smmuv3: Add page table walk for stage-2
  hw/arm/smmuv3: Parse STE config for stage-2
  hw/arm/smmuv3: Make TLB lookup work for stage-2
  hw/arm/smmuv3: Add VMID to TLB tagging
  hw/arm/smmuv3: Add CMDs related to stage-2
  hw/arm/smmuv3: Add stage-2 support in iova notifier
  hw/arm/smmuv3: Add knob to choose translation stage and enable stage-2

Peter Maydell (1):
  target/arm: Explicitly select short-format FSR for M-profile

Thomas Huth (1):
  tests/qtest: Run arm-specific tests only if the required machine is 
available

Tommy Wu (1):
  hw/dma/xilinx_axidma: Check DMASR.HALTED to prevent infinite loop.

Vitaly Cheptsov (1):
  fsl-imx6: Add SNVS support for i.MX6 boards

 docs/conf.py|   2 +-
 docs/system/arm/sbsa.rst|   2 +-
 configs/devices/aarch64-softmmu/default.mak |   6 +
 configs/devices/arm-softmmu/default.mak |  40 
 hw/arm/smmu-internal.h  |  37 +++
 hw/arm/smmuv3-internal.h|  12 +-
 include/hw/arm/fsl-imx6.h   |   2 +
 include/hw/arm/smmu-common.h|  45 +++-
 include/hw/arm/smmuv3.h |   4 +
 include/qemu/help-texts.h   |   2 +-
 hw/arm/fsl-imx6.c   |   8 +
 hw/arm/sbsa-ref.c   |  19 +-
 hw/arm/smmu-common.c| 209 ++--
 hw/arm/smmuv3.c | 357 
 hw/arm/xlnx-zynqmp.c|   2 +-
 hw/dma/xilinx_axidma.c  |  11 +-
 target/arm/tcg/tlb_helper.c |  13 +-
 hw/arm/Kconfig  | 123 ++
 hw/arm/trace-events |  14 +-
 target/arm/Kconfig  |   3 +
 tests/qtest/meson.build |   7 +-
 21 files changed, 773 insertions(+), 145 deletions(-)

Re: [PULL 00/21] target-arm queue

[Peter Maydell]

On Fri, 21 Apr 2023 at 11:49, Richard Henderson
 wrote:
> Applied, thanks.  Please update https://wiki.qemu.org/ChangeLog/7.1 as 
> appropriate.

8.1 :-)  (I created the 8.1 page yesterday.)

-- PMM

Re: [PULL 00/21] target-arm queue

[Richard Henderson]

On 4/20/23 11:04, Peter Maydell wrote:

Hi; here's the first target-arm pullreq for the 8.1 cycle.
Nothing particularly huge in here, just the various things
that had accumulated during the freeze.

thanks
-- PMM

The following changes since commit 2d82c32b2ceaca3dc3da5e36e10976f34bfcb598:

   Open 8.1 development tree (2023-04-20 10:05:25 +0100)

are available in the Git repository at:

   https://git.linaro.org/people/pmaydell/qemu-arm.git 
tags/pull-target-arm-20230420

for you to fetch changes up to 1ed1f338520cda0574b7e04f5e8e85e049740548:

   arm/mcimx7d-sabre: Set fec2-phy-connected property to false (2023-04-20 
10:46:43 +0100)


target-arm queue:
  * hw/arm: Fix some typos in comments (most found by codespell)
  * exynos: Fix out-of-bounds access in exynos4210_gcomp_find debug printf
  * Orangepi-PC, Cubieboard: add Allwinner WDT watchdog emulation
  * tests/avocado: Add reboot tests to Cubieboard
  * hw/timer/imx_epit: Fix bugs in timer limit checking
  * target/arm: Remove KVM AArch32 CPU definitions
  * hw/arm/virt: Restrict Cortex-A7 check to TCG
  * target/arm: Initialize debug capabilities only once
  * target/arm: Implement FEAT_PAN3
  * docs/devel/kconfig.rst: Fix incorrect markup
  * target/arm: Report pauth information to gdb as 'pauth_v2'
  * mcimxd7-sabre, mcimx6ul-evk: Correctly model the way the PHY
on the second ethernet device must be configured via the
first one


Applied, thanks.  Please update https://wiki.qemu.org/ChangeLog/7.1 as 
appropriate.


r~

[PULL 00/21] target-arm queue

[Peter Maydell]

Hi; here's the first target-arm pullreq for the 8.1 cycle.
Nothing particularly huge in here, just the various things
that had accumulated during the freeze.

thanks
-- PMM

The following changes since commit 2d82c32b2ceaca3dc3da5e36e10976f34bfcb598:

  Open 8.1 development tree (2023-04-20 10:05:25 +0100)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git 
tags/pull-target-arm-20230420

for you to fetch changes up to 1ed1f338520cda0574b7e04f5e8e85e049740548:

  arm/mcimx7d-sabre: Set fec2-phy-connected property to false (2023-04-20 
10:46:43 +0100)


target-arm queue:
 * hw/arm: Fix some typos in comments (most found by codespell)
 * exynos: Fix out-of-bounds access in exynos4210_gcomp_find debug printf
 * Orangepi-PC, Cubieboard: add Allwinner WDT watchdog emulation
 * tests/avocado: Add reboot tests to Cubieboard
 * hw/timer/imx_epit: Fix bugs in timer limit checking
 * target/arm: Remove KVM AArch32 CPU definitions
 * hw/arm/virt: Restrict Cortex-A7 check to TCG
 * target/arm: Initialize debug capabilities only once
 * target/arm: Implement FEAT_PAN3
 * docs/devel/kconfig.rst: Fix incorrect markup
 * target/arm: Report pauth information to gdb as 'pauth_v2'
 * mcimxd7-sabre, mcimx6ul-evk: Correctly model the way the PHY
   on the second ethernet device must be configured via the
   first one


Akihiko Odaki (1):
  target/arm: Initialize debug capabilities only once

Axel Heider (2):
  hw/timer/imx_epit: don't shadow variable
  hw/timer/imx_epit: fix limit check

Feng Jiang (1):
  exynos: Fix out-of-bounds access in exynos4210_gcomp_find debug printf

Guenter Roeck (5):
  hw/net/imx_fec: Support two Ethernet interfaces connected to single MDIO 
bus
  fsl-imx6ul: Add fec[12]-phy-connected properties
  arm/mcimx6ul-evk: Set fec1-phy-connected property to false
  fsl-imx7: Add fec[12]-phy-connected properties
  arm/mcimx7d-sabre: Set fec2-phy-connected property to false

Peter Maydell (5):
  target/arm: Pass ARMMMUFaultInfo to merge_syn_data_abort()
  target/arm: Don't set ISV when reporting stage 1 faults in ESR_EL2
  target/arm: Implement FEAT_PAN3
  docs/devel/kconfig.rst: Fix incorrect markup
  target/arm: Report pauth information to gdb as 'pauth_v2'

Philippe Mathieu-Daudé (2):
  target/arm: Remove KVM AArch32 CPU definitions
  hw/arm/virt: Restrict Cortex-A7 check to TCG

Stefan Weil (1):
  hw/arm: Fix some typos in comments (most found by codespell)

Strahinja Jankovic (4):
  hw/watchdog: Allwinner WDT emulation for system reset
  hw/arm: Add WDT to Allwinner-A10 and Cubieboard
  hw/arm: Add WDT to Allwinner-H3 and Orangepi-PC
  tests/avocado: Add reboot tests to Cubieboard

 docs/devel/kconfig.rst  |   2 +-
 docs/system/arm/cubieboard.rst  |   1 +
 docs/system/arm/emulation.rst   |   1 +
 docs/system/arm/orangepi.rst|   1 +
 include/hw/arm/allwinner-a10.h  |   2 +
 include/hw/arm/allwinner-h3.h   |   5 +-
 include/hw/arm/fsl-imx6ul.h |   1 +
 include/hw/arm/fsl-imx7.h   |   1 +
 include/hw/net/imx_fec.h|   2 +
 include/hw/watchdog/allwinner-wdt.h | 123 +++
 target/arm/cpu.h|   5 +
 target/arm/kvm-consts.h |   9 +-
 target/arm/kvm_arm.h|   8 +
 hw/arm/allwinner-a10.c  |   7 +
 hw/arm/allwinner-h3.c   |   8 +
 hw/arm/exynos4210.c |   4 +-
 hw/arm/fsl-imx6ul.c |  20 ++
 hw/arm/fsl-imx7.c   |  20 ++
 hw/arm/mcimx6ul-evk.c   |   2 +
 hw/arm/mcimx7d-sabre.c  |   2 +
 hw/arm/musicpal.c   |   2 +-
 hw/arm/omap1.c  |   2 +-
 hw/arm/omap2.c  |   2 +-
 hw/arm/virt-acpi-build.c|   2 +-
 hw/arm/virt.c   |   4 +-
 hw/arm/xlnx-versal-virt.c   |   2 +-
 hw/net/imx_fec.c|  27 ++-
 hw/timer/exynos4210_mct.c   |  13 +-
 hw/timer/imx_epit.c |   2 +-
 hw/watchdog/allwinner-wdt.c | 416 
 target/arm/cpu64.c  |   2 +-
 target/arm/cpu_tcg.c|   2 -
 target/arm/gdbstub.c|   9 +-
 target/arm/kvm.c|   2 +
 target/arm/kvm64.c  |  18 +-
 target/arm/ptw.c|  14 +-
 target/arm/tcg/tlb_helper.c |  26 ++-
 gdb-xml/aarch64-pauth.xml   |   2 +-
 hw/arm/Kconfig  |   4 +-
 hw/watchdog/Kconfig |   4 +
 hw/watchdog/meson.build |   1 +
 hw/watchdog/trace-events|   7 +
 tests/avocado/boot_linux_console.py |  15 +-
 43 files changed, 738 insertions(+), 64 deletions(-)
 create mode 100644 

Re: [PULL 00/21] target-arm queue

[Peter Maydell]

On Mon, 6 Mar 2023 at 15:34, Peter Maydell  wrote:
>
> The following changes since commit f003dd8d81f7d88f4b1f8802309eaa76f6eb223a:
>
>   Merge tag 'pull-tcg-20230305' of https://gitlab.com/rth7680/qemu into 
> staging (2023-03-06 10:20:04 +)
>
> are available in the Git repository at:
>
>   https://git.linaro.org/people/pmaydell/qemu-arm.git 
> tags/pull-target-arm-20230306
>
> for you to fetch changes up to 2ddc45954f97cd1d7ee5cbca0def05e980d1da9f:
>
>   hw: arm: allwinner-h3: Fix and complete H3 i2c devices (2023-03-06 15:31:24 
> +)
>
> 
> target-arm queue:
>  * allwinner-h3: Fix I2C controller model for Sun6i SoCs
>  * allwinner-h3: Add missing i2c controllers
>  * Expose M-profile system registers to gdbstub
>  * Expose pauth information to gdbstub
>  * Support direct boot for Linux/arm64 EFI zboot images
>  * Fix incorrect stage 2 MMU setup validation
>
> 


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/8.0
for any user-visible changes.

-- PMM

[PULL 00/21] target-arm queue

[Peter Maydell]

The following changes since commit f003dd8d81f7d88f4b1f8802309eaa76f6eb223a:

  Merge tag 'pull-tcg-20230305' of https://gitlab.com/rth7680/qemu into staging 
(2023-03-06 10:20:04 +)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git 
tags/pull-target-arm-20230306

for you to fetch changes up to 2ddc45954f97cd1d7ee5cbca0def05e980d1da9f:

  hw: arm: allwinner-h3: Fix and complete H3 i2c devices (2023-03-06 15:31:24 
+)


target-arm queue:
 * allwinner-h3: Fix I2C controller model for Sun6i SoCs
 * allwinner-h3: Add missing i2c controllers
 * Expose M-profile system registers to gdbstub
 * Expose pauth information to gdbstub
 * Support direct boot for Linux/arm64 EFI zboot images
 * Fix incorrect stage 2 MMU setup validation


Ard Biesheuvel (1):
  hw: arm: Support direct boot for Linux/arm64 EFI zboot images

David Reiss (2):
  target/arm: Export arm_v7m_mrs_control
  target/arm: Export arm_v7m_get_sp_ptr

Richard Henderson (16):
  target/arm: Normalize aarch64 gdbstub get/set function names
  target/arm: Unexport arm_gen_dynamic_sysreg_xml
  target/arm: Move arm_gen_dynamic_svereg_xml to gdbstub64.c
  target/arm: Split out output_vector_union_type
  target/arm: Simplify register counting in arm_gen_dynamic_svereg_xml
  target/arm: Hoist pred_width in arm_gen_dynamic_svereg_xml
  target/arm: Fix svep width in arm_gen_dynamic_svereg_xml
  target/arm: Add name argument to output_vector_union_type
  target/arm: Simplify iteration over bit widths
  target/arm: Create pauth_ptr_mask
  target/arm: Implement gdbstub pauth extension
  target/arm: Implement gdbstub m-profile systemreg and secext
  target/arm: Handle m-profile in arm_is_secure
  target/arm: Stub arm_hcr_el2_eff for m-profile
  target/arm: Diagnose incorrect usage of arm_is_secure subroutines
  target/arm: Rewrite check_s2_mmu_setup

qianfan Zhao (2):
  hw: allwinner-i2c: Fix TWI_CNTR_INT_FLAG on SUN6i SoCs
  hw: arm: allwinner-h3: Fix and complete H3 i2c devices

 configs/targets/aarch64-linux-user.mak|   2 +-
 configs/targets/aarch64-softmmu.mak   |   2 +-
 configs/targets/aarch64_be-linux-user.mak |   2 +-
 include/hw/arm/allwinner-h3.h |   6 +
 include/hw/i2c/allwinner-i2c.h|   6 +
 include/hw/loader.h   |  19 ++
 target/arm/cpu.h  |  17 +-
 target/arm/internals.h|  34 +++-
 hw/arm/allwinner-h3.c |  29 +++-
 hw/arm/boot.c |   6 +
 hw/core/loader.c  |  91 ++
 hw/i2c/allwinner-i2c.c|  26 ++-
 target/arm/gdbstub.c  | 278 ++
 target/arm/gdbstub64.c| 175 ++-
 target/arm/helper.c   |   3 +
 target/arm/ptw.c  | 173 +++
 target/arm/tcg/m_helper.c |  90 +-
 target/arm/tcg/pauth_helper.c |  26 ++-
 gdb-xml/aarch64-pauth.xml |  15 ++
 19 files changed, 742 insertions(+), 258 deletions(-)
 create mode 100644 gdb-xml/aarch64-pauth.xml

Re: [PULL 00/21] target-arm queue

[Peter Maydell]

On Fri, 18 Mar 2022 at 13:23, Peter Maydell  wrote:
>
> Mostly straightforward bugfixes. The new Xilinx devices are
> arguably 'new feature', but they're fixing a regression where
> our changes to PSCI in commit 3f37979bf mean that EL3 guest
> code now needs to talk to a proper emulated power-controller
> device to turn on secondary CPUs; and it's not yet rc1 and
> they only affect the Xilinx board, so it seems OK to me.
>
> thanks
> -- PMM
>
> The following changes since commit 1d60bb4b14601e38ed17384277aa4c30c57925d3:
>
>   Merge tag 'pull-request-2022-03-15v2' of https://gitlab.com/thuth/qemu into 
> staging (2022-03-16 10:43:58 +)
>
> are available in the Git repository at:
>
>   https://git.linaro.org/people/pmaydell/qemu-arm.git 
> tags/pull-target-arm-20220318
>
> for you to fetch changes up to 79d54c9eac04c554e3c081589542f801ace71797:
>
>   util/osdep: Remove some early cruft (2022-03-18 11:32:13 +)
>
> 
> target-arm queue:
>  * Fix sve2 ldnt1 and stnt1
>  * Fix pauth_check_trap vs SEL2
>  * Fix handling of LPAE block descriptors
>  * hw/dma/xlnx_csu_dma: Set TYPE_XLNX_CSU_DMA class_size
>  * hw/misc/npcm7xx_clk: Don't leak string in npcm7xx_clk_sel_init()
>  * nsis installer: List emulators in alphabetical order
>  * nsis installer: Suppress "ANSI targets are deprecated" warning
>  * nsis installer: Fix mouse-over descriptions for emulators
>  * hw/arm/virt: Fix gic-version=max when CONFIG_ARM_GICV3_TCG is unset
>  * Improve M-profile vector table access logging
>  * Xilinx ZynqMP: model CRF and APU control
>  * Fix compile issues on modern Solaris
>


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/7.0
for any user-visible changes.

-- PMM

[PULL 00/21] target-arm queue

[Peter Maydell]

Mostly straightforward bugfixes. The new Xilinx devices are
arguably 'new feature', but they're fixing a regression where
our changes to PSCI in commit 3f37979bf mean that EL3 guest
code now needs to talk to a proper emulated power-controller
device to turn on secondary CPUs; and it's not yet rc1 and
they only affect the Xilinx board, so it seems OK to me.

thanks
-- PMM

The following changes since commit 1d60bb4b14601e38ed17384277aa4c30c57925d3:

  Merge tag 'pull-request-2022-03-15v2' of https://gitlab.com/thuth/qemu into 
staging (2022-03-16 10:43:58 +)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git 
tags/pull-target-arm-20220318

for you to fetch changes up to 79d54c9eac04c554e3c081589542f801ace71797:

  util/osdep: Remove some early cruft (2022-03-18 11:32:13 +)


target-arm queue:
 * Fix sve2 ldnt1 and stnt1
 * Fix pauth_check_trap vs SEL2
 * Fix handling of LPAE block descriptors
 * hw/dma/xlnx_csu_dma: Set TYPE_XLNX_CSU_DMA class_size
 * hw/misc/npcm7xx_clk: Don't leak string in npcm7xx_clk_sel_init()
 * nsis installer: List emulators in alphabetical order
 * nsis installer: Suppress "ANSI targets are deprecated" warning
 * nsis installer: Fix mouse-over descriptions for emulators
 * hw/arm/virt: Fix gic-version=max when CONFIG_ARM_GICV3_TCG is unset
 * Improve M-profile vector table access logging
 * Xilinx ZynqMP: model CRF and APU control
 * Fix compile issues on modern Solaris


Andrew Deason (3):
  util/osdep: Avoid madvise proto on modern Solaris
  hw/i386/acpi-build: Avoid 'sun' identifier
  util/osdep: Remove some early cruft

Edgar E. Iglesias (6):
  hw/arm/xlnx-zynqmp: Add an unimplemented SERDES area
  target/arm: Make rvbar settable after realize
  hw/misc: Add a model of the Xilinx ZynqMP CRF
  hw/arm/xlnx-zynqmp: Connect the ZynqMP CRF
  hw/misc: Add a model of the Xilinx ZynqMP APU Control
  hw/arm/xlnx-zynqmp: Connect the ZynqMP APU Control

Eric Auger (2):
  hw/intc: Rename CONFIG_ARM_GIC_TCG into CONFIG_ARM_GICV3_TCG
  hw/arm/virt: Fix gic-version=max when CONFIG_ARM_GICV3_TCG is unset

Peter Maydell (8):
  target/arm: Fix handling of LPAE block descriptors
  hw/dma/xlnx_csu_dma: Set TYPE_XLNX_CSU_DMA class_size
  hw/misc/npcm7xx_clk: Don't leak string in npcm7xx_clk_sel_init()
  nsis installer: List emulators in alphabetical order
  nsis installer: Suppress "ANSI targets are deprecated" warning
  nsis installer: Fix mouse-over descriptions for emulators
  target/arm: Log M-profile vector table accesses
  target/arm: Log fault address for M-profile faults

Richard Henderson (2):
  target/arm: Fix sve2 ldnt1 and stnt1
  target/arm: Fix pauth_check_trap vs SEL2

 meson.build|  23 ++-
 include/hw/arm/xlnx-zynqmp.h   |   4 +
 include/hw/misc/xlnx-zynqmp-apu-ctrl.h |  93 
 include/hw/misc/xlnx-zynqmp-crf.h  | 211 ++
 include/qemu/osdep.h   |   8 +
 target/arm/cpu.h   |   3 +-
 target/arm/sve.decode  |   5 +-
 hw/arm/virt.c  |   7 +-
 hw/arm/xlnx-zynqmp.c   |  46 +-
 hw/dma/xlnx_csu_dma.c  |   1 +
 hw/i386/acpi-build.c   |   4 +-
 hw/misc/npcm7xx_clk.c  |   4 +-
 hw/misc/xlnx-zynqmp-apu-ctrl.c | 253 +++
 hw/misc/xlnx-zynqmp-crf.c  | 266 +
 target/arm/cpu.c   |  17 ++-
 target/arm/helper.c|  20 ++-
 target/arm/m_helper.c  |  11 ++
 target/arm/pauth_helper.c  |   2 +-
 target/arm/translate-sve.c |  51 ++-
 tests/tcg/aarch64/test-826.c   |  50 +++
 util/osdep.c   |  10 --
 hw/intc/Kconfig|   2 +-
 hw/intc/meson.build|   4 +-
 hw/misc/meson.build|   2 +
 qemu.nsi   |   8 +-
 scripts/nsis.py|  17 ++-
 tests/tcg/aarch64/Makefile.target  |   4 +
 tests/tcg/configure.sh |   4 +
 28 files changed, 1084 insertions(+), 46 deletions(-)
 create mode 100644 include/hw/misc/xlnx-zynqmp-apu-ctrl.h
 create mode 100644 include/hw/misc/xlnx-zynqmp-crf.h
 create mode 100644 hw/misc/xlnx-zynqmp-apu-ctrl.c
 create mode 100644 hw/misc/xlnx-zynqmp-crf.c
 create mode 100644 tests/tcg/aarch64/test-826.c

Re: [PULL 00/21] target-arm queue

[Peter Maydell]

On Mon, 2 Aug 2021 at 12:58, Peter Maydell  wrote:
>
> A largish pullreq but it's almost all docs fixes.
>
> -- PMM
>
> The following changes since commit 10a3c4a4b3e14208cfed274514d1911e5230935f:
>
>   Merge remote-tracking branch 'remotes/jasowang/tags/net-pull-request' into 
> staging (2021-08-02 09:47:07 +0100)
>
> are available in the Git repository at:
>
>   https://git.linaro.org/people/pmaydell/qemu-arm.git 
> tags/pull-target-arm-20210802
>
> for you to fetch changes up to 4a64939db76b10d8d41d2af3c6aad8142da55450:
>
>   docs: Move user-facing barrier docs into system manual (2021-08-02 12:55:51 
> +0100)
>
> 
> target-arm queue:
>  * Add documentation of Arm 'mainstone', 'kzm', 'imx25-pdk' boards
>  * MAINTAINERS: Don't list Andrzej Zaborowski for various components
>  * docs: Remove stale TODO comments about license and version
>  * docs: Move licence/copyright from HTML output to rST comments
>  * docs: Format literal text correctly
>  * hw/arm/boot: Report error if there is no fw_cfg device in the machine
>  * docs: rSTify barrier.txt and bootindex.txt


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/6.1
for any user-visible changes.

-- PMM

[PULL 00/21] target-arm queue

[Peter Maydell]

A largish pullreq but it's almost all docs fixes.

-- PMM

The following changes since commit 10a3c4a4b3e14208cfed274514d1911e5230935f:

  Merge remote-tracking branch 'remotes/jasowang/tags/net-pull-request' into 
staging (2021-08-02 09:47:07 +0100)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git 
tags/pull-target-arm-20210802

for you to fetch changes up to 4a64939db76b10d8d41d2af3c6aad8142da55450:

  docs: Move user-facing barrier docs into system manual (2021-08-02 12:55:51 
+0100)


target-arm queue:
 * Add documentation of Arm 'mainstone', 'kzm', 'imx25-pdk' boards
 * MAINTAINERS: Don't list Andrzej Zaborowski for various components
 * docs: Remove stale TODO comments about license and version
 * docs: Move licence/copyright from HTML output to rST comments
 * docs: Format literal text correctly
 * hw/arm/boot: Report error if there is no fw_cfg device in the machine
 * docs: rSTify barrier.txt and bootindex.txt


Peter Maydell (21):
  docs: Add documentation of Arm 'mainstone' board
  docs: Add documentation of Arm 'kzm' board
  docs: Add documentation of Arm 'imx25-pdk' board
  MAINTAINERS: Don't list Andrzej Zaborowski for various components
  docs: Remove stale TODO comments about license and version
  docs: Move licence/copyright from HTML output to rST comments
  docs/devel/build-system.rst: Format literals correctly
  docs/devel/build-system.rst: Correct typo in example code
  docs/devel/ebpf_rss.rst: Format literals correctly
  docs/devel/migration.rst: Format literals correctly
  docs/devel: Format literals correctly
  docs/system/s390x/protvirt.rst: Format literals correctly
  docs/system/arm/cpu-features.rst: Format literals correctly
  docs: Format literals correctly
  docs/about/removed-features: Fix markup error
  docs/tools/virtiofsd.rst: Delete stray backtick
  hw/arm/boot: Report error if there is no fw_cfg device in the machine
  docs: Move bootindex.txt into system section and rstify
  docs: Move the protocol part of barrier.txt into interop
  ui/input-barrier: Move TODOs from barrier.txt to a comment
  docs: Move user-facing barrier docs into system manual

 docs/about/index.rst |   2 +-
 docs/about/removed-features.rst  |   2 +-
 docs/barrier.txt | 370 ---
 docs/bootindex.txt   |  52 
 docs/devel/build-system.rst  | 160 +-
 docs/devel/ebpf_rss.rst  |  18 +-
 docs/devel/migration.rst |  36 +--
 docs/devel/qgraph.rst|   8 +-
 docs/devel/tcg-plugins.rst   |  14 +-
 docs/devel/testing.rst   |   8 +-
 docs/interop/barrier.rst | 426 +++
 docs/interop/index.rst   |   1 +
 docs/interop/live-block-operations.rst   |   2 +-
 docs/interop/qemu-ga-ref.rst |   9 -
 docs/interop/qemu-qmp-ref.rst|   9 -
 docs/interop/qemu-storage-daemon-qmp-ref.rst |   9 -
 docs/interop/vhost-user-gpu.rst  |   7 +-
 docs/interop/vhost-user.rst  |  12 +-
 docs/system/arm/cpu-features.rst | 116 
 docs/system/arm/imx25-pdk.rst|  19 ++
 docs/system/arm/kzm.rst  |  18 ++
 docs/system/arm/mainstone.rst|  25 ++
 docs/system/arm/nuvoton.rst  |   2 +-
 docs/system/arm/sbsa.rst |   4 +-
 docs/system/arm/virt.rst |   2 +-
 docs/system/barrier.rst  |  44 +++
 docs/system/bootindex.rst|  76 +
 docs/system/cpu-hotplug.rst  |   2 +-
 docs/system/generic-loader.rst   |   4 +-
 docs/system/guest-loader.rst |   6 +-
 docs/system/index.rst|   2 +
 docs/system/ppc/powernv.rst  |   8 +-
 docs/system/riscv/microchip-icicle-kit.rst   |   2 +-
 docs/system/riscv/virt.rst   |   2 +-
 docs/system/s390x/protvirt.rst   |  12 +-
 docs/system/target-arm.rst   |   3 +
 docs/tools/virtiofsd.rst |   2 +-
 hw/arm/boot.c|   9 +
 hw/arm/sbsa-ref.c|   7 -
 ui/input-barrier.c   |   5 +
 MAINTAINERS  |   8 +-
 41 files changed, 849 insertions(+), 674 deletions(-)
 delete mode 100644 docs/barrier.txt
 delete mode 100644 docs/bootindex.txt
 create mode 100644 docs/interop/barrier.rst
 create mode 100644 docs/system/arm/imx25-pdk.rst
 create mode 100644 docs/system/arm/kzm.rst
 create mode 100644 

Re: [PULL 00/21] target-arm queue

[P J P]

+-- On Wed, 3 Feb 2021, Philippe Mathieu-Daudé wrote --+
| FYI Prasad mentioned a CVE was requested:
| https://www.mail-archive.com/qemu-devel@nongnu.org/msg778659.html
| 
| As you said it is an odd configuration, I am not sure it is worth
| to wait for the CVE number to add it to the commit (which helps
| downstream distributions tracking these).
| 
| [updating]
| 
| Just got detail from Prasad on IRC, it usually takes ~1 day to get
| the CVE number assigned, so maybe worth postponing this until tomorrow.
| 
| Prasad, can you reply to this message ASAP once you get the number?

'CVE-2021-20221' assigned by Red Hat Inc.
  -> https://bugs.launchpad.net/qemu/+bug/1914353/comments/3

Thank you.
--
Prasad J Pandit / Red Hat Product Security Team
8685 545E B54C 486B C6EB 271E E285 8B5A F050 DE8D

Re: [PULL 00/21] target-arm queue

[Philippe Mathieu-Daudé]

Hi Peter,

On 2/2/21 6:54 PM, Peter Maydell wrote:
> Mostly just bug fixes. The important one here is
>   hw/intc/arm_gic: Fix interrupt ID in GICD_SGIR register
> which fixes a buffer overrun that's a security issue if you're running
> KVM on Arm with kernel-irqchip=off (which hopefully nobody is doing in
> a security context, because kernel-irqchip=on is the default and the
> sensible choice for performance).

FYI Prasad mentioned a CVE was requested:
https://www.mail-archive.com/qemu-devel@nongnu.org/msg778659.html

As you said it is an odd configuration, I am not sure it is worth
to wait for the CVE number to add it to the commit (which helps
downstream distributions tracking these).

[updating]

Just got detail from Prasad on IRC, it usually takes ~1 day to get
the CVE number assigned, so maybe worth postponing this until tomorrow.

Prasad, can you reply to this message ASAP once you get the number?

Thanks,

Phil.

> -- PMM
> 
> The following changes since commit cf7ca7d5b9faca13f1f8e3ea92cfb2f741eb0c0e:
> 
>   Merge remote-tracking branch 
> 'remotes/stefanha-gitlab/tags/tracing-pull-request' into staging (2021-02-01 
> 16:28:00 +)
> 
> are available in the Git repository at:
> 
>   https://git.linaro.org/people/pmaydell/qemu-arm.git 
> tags/pull-target-arm-20210202-1
> 
> for you to fetch changes up to 14657850c9cc10948551fbb884c30eb5a3a7370a:
> 
>   hw/arm: Display CPU type in machine description (2021-02-02 17:53:44 +)
> 
> 
> target-arm queue:
>  * hw/intc/arm_gic: Allow to use QTest without crashing
>  * hw/char/exynos4210_uart: Fix buffer size reporting with FIFO disabled
>  * hw/char/exynos4210_uart: Fix missing call to report ready for input
>  * hw/arm/smmuv3: Fix addr_mask for range-based invalidation
>  * hw/ssi/imx_spi: Fix various minor bugs
>  * hw/intc/arm_gic: Fix interrupt ID in GICD_SGIR register
>  * hw/arm: Add missing Kconfig dependencies
>  * hw/arm: Display CPU type in machine description
> 
> 
> Bin Meng (5):
>   hw/ssi: imx_spi: Use a macro for number of chip selects supported
>   hw/ssi: imx_spi: Remove imx_spi_update_irq() in imx_spi_reset()
>   hw/ssi: imx_spi: Round up the burst length to be multiple of 8
>   hw/ssi: imx_spi: Correct the burst length > 32 bit transfer logic
>   hw/ssi: imx_spi: Correct tx and rx fifo endianness
> 
> Iris Johnson (2):
>   hw/char/exynos4210_uart: Fix buffer size reporting with FIFO disabled
>   hw/char/exynos4210_uart: Fix missing call to report ready for input
> 
> Philippe Mathieu-Daudé (12):
>   hw/intc/arm_gic: Allow to use QTest without crashing
>   hw/ssi: imx_spi: Remove pointless variable initialization
>   hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register value
>   hw/ssi: imx_spi: Rework imx_spi_read() to handle block disabled
>   hw/ssi: imx_spi: Rework imx_spi_write() to handle block disabled
>   hw/intc/arm_gic: Fix interrupt ID in GICD_SGIR register
>   hw/arm/stm32f405_soc: Add missing dependency on OR_IRQ
>   hw/arm/exynos4210: Add missing dependency on OR_IRQ
>   hw/arm/xlnx-versal: Versal SoC requires ZDMA
>   hw/arm/xlnx-versal: Versal SoC requires ZynqMP peripherals
>   hw/net/can: ZynqMP CAN device requires PTIMER
>   hw/arm: Display CPU type in machine description
> 
> Xuzhou Cheng (1):
>   hw/ssi: imx_spi: Disable chip selects when controller is disabled
> 
> Zenghui Yu (1):
>   hw/arm/smmuv3: Fix addr_mask for range-based invalidation
> 
>  include/hw/ssi/imx_spi.h  |   5 +-
>  hw/arm/digic_boards.c |   2 +-
>  hw/arm/microbit.c |   2 +-
>  hw/arm/netduino2.c|   2 +-
>  hw/arm/netduinoplus2.c|   2 +-
>  hw/arm/orangepi.c |   2 +-
>  hw/arm/smmuv3.c   |   4 +-
>  hw/arm/stellaris.c|   4 +-
>  hw/char/exynos4210_uart.c |   7 ++-
>  hw/intc/arm_gic.c |   5 +-
>  hw/ssi/imx_spi.c  | 153 
> +-
>  hw/Kconfig|   1 +
>  hw/arm/Kconfig|   5 ++
>  hw/dma/Kconfig|   3 +
>  hw/dma/meson.build|   2 +-
>  15 files changed, 130 insertions(+), 69 deletions(-)
> 

[PULL 00/21] target-arm queue

[Peter Maydell]

Mostly just bug fixes. The important one here is
  hw/intc/arm_gic: Fix interrupt ID in GICD_SGIR register
which fixes a buffer overrun that's a security issue if you're running
KVM on Arm with kernel-irqchip=off (which hopefully nobody is doing in
a security context, because kernel-irqchip=on is the default and the
sensible choice for performance).

-- PMM

The following changes since commit cf7ca7d5b9faca13f1f8e3ea92cfb2f741eb0c0e:

  Merge remote-tracking branch 
'remotes/stefanha-gitlab/tags/tracing-pull-request' into staging (2021-02-01 
16:28:00 +)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git 
tags/pull-target-arm-20210202-1

for you to fetch changes up to 14657850c9cc10948551fbb884c30eb5a3a7370a:

  hw/arm: Display CPU type in machine description (2021-02-02 17:53:44 +)


target-arm queue:
 * hw/intc/arm_gic: Allow to use QTest without crashing
 * hw/char/exynos4210_uart: Fix buffer size reporting with FIFO disabled
 * hw/char/exynos4210_uart: Fix missing call to report ready for input
 * hw/arm/smmuv3: Fix addr_mask for range-based invalidation
 * hw/ssi/imx_spi: Fix various minor bugs
 * hw/intc/arm_gic: Fix interrupt ID in GICD_SGIR register
 * hw/arm: Add missing Kconfig dependencies
 * hw/arm: Display CPU type in machine description


Bin Meng (5):
  hw/ssi: imx_spi: Use a macro for number of chip selects supported
  hw/ssi: imx_spi: Remove imx_spi_update_irq() in imx_spi_reset()
  hw/ssi: imx_spi: Round up the burst length to be multiple of 8
  hw/ssi: imx_spi: Correct the burst length > 32 bit transfer logic
  hw/ssi: imx_spi: Correct tx and rx fifo endianness

Iris Johnson (2):
  hw/char/exynos4210_uart: Fix buffer size reporting with FIFO disabled
  hw/char/exynos4210_uart: Fix missing call to report ready for input

Philippe Mathieu-Daudé (12):
  hw/intc/arm_gic: Allow to use QTest without crashing
  hw/ssi: imx_spi: Remove pointless variable initialization
  hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register value
  hw/ssi: imx_spi: Rework imx_spi_read() to handle block disabled
  hw/ssi: imx_spi: Rework imx_spi_write() to handle block disabled
  hw/intc/arm_gic: Fix interrupt ID in GICD_SGIR register
  hw/arm/stm32f405_soc: Add missing dependency on OR_IRQ
  hw/arm/exynos4210: Add missing dependency on OR_IRQ
  hw/arm/xlnx-versal: Versal SoC requires ZDMA
  hw/arm/xlnx-versal: Versal SoC requires ZynqMP peripherals
  hw/net/can: ZynqMP CAN device requires PTIMER
  hw/arm: Display CPU type in machine description

Xuzhou Cheng (1):
  hw/ssi: imx_spi: Disable chip selects when controller is disabled

Zenghui Yu (1):
  hw/arm/smmuv3: Fix addr_mask for range-based invalidation

 include/hw/ssi/imx_spi.h  |   5 +-
 hw/arm/digic_boards.c |   2 +-
 hw/arm/microbit.c |   2 +-
 hw/arm/netduino2.c|   2 +-
 hw/arm/netduinoplus2.c|   2 +-
 hw/arm/orangepi.c |   2 +-
 hw/arm/smmuv3.c   |   4 +-
 hw/arm/stellaris.c|   4 +-
 hw/char/exynos4210_uart.c |   7 ++-
 hw/intc/arm_gic.c |   5 +-
 hw/ssi/imx_spi.c  | 153 +-
 hw/Kconfig|   1 +
 hw/arm/Kconfig|   5 ++
 hw/dma/Kconfig|   3 +
 hw/dma/meson.build|   2 +-
 15 files changed, 130 insertions(+), 69 deletions(-)

[PULL 00/21] target-arm queue

[Peter Maydell]

Arm queue; not huge but I figured I might as well send it out since
I've been doing code review today and there's no queue of unprocessed
pullreqs...

thanks
-- PMM

The following changes since commit b3f846c59d8405bb87c551187721fc92ff2f1b92:

  Merge remote-tracking branch 
'remotes/huth-gitlab/tags/pull-request-2021-01-11v2' into staging (2021-01-11 
15:15:35 +)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git 
tags/pull-target-arm-20210112

for you to fetch changes up to 19d131395ccaf503db21dadd8257e6dc9fc1d7de:

  ui/cocoa: Fix openFile: deprecation on Big Sur (2021-01-12 11:38:37 +)


target-arm queue:
 * arm: Support emulation of ARMv8.4-TTST extension
 * arm: Update cpu.h ID register field definitions
 * arm: Fix breakage of XScale instruction emulation
 * hw/net/lan9118: Fix RX Status FIFO PEEK value
 * npcm7xx: Add ADC and PWM emulation
 * ui/cocoa: Make "open docs" help menu entry work again when binary
   is run from the build tree
 * ui/cocoa: Fix openFile: deprecation on Big Sur
 * docs: Add qemu-storage-daemon(1) manpage to meson.build
 * docs: Build and install all the docs in a single manual


Hao Wu (6):
  hw/misc: Add clock converter in NPCM7XX CLK module
  hw/timer: Refactor NPCM7XX Timer to use CLK clock
  hw/adc: Add an ADC module for NPCM7XX
  hw/misc: Add a PWM module for NPCM7XX
  hw/misc: Add QTest for NPCM7XX PWM Module
  hw/*: Use type casting for SysBusDevice in NPCM7XX

Leif Lindholm (6):
  target/arm: fix typo in cpu.h ID_AA64PFR1 field name
  target/arm: make ARMCPU.clidr 64-bit
  target/arm: make ARMCPU.ctr 64-bit
  target/arm: add descriptions of CLIDR_EL1, CCSIDR_EL1, CTR_EL0 to cpu.h
  target/arm: add aarch64 ID register fields to cpu.h
  target/arm: add aarch32 ID register fields to cpu.h

Peter Maydell (5):
  docs: Add qemu-storage-daemon(1) manpage to meson.build
  docs: Build and install all the docs in a single manual
  target/arm: Don't decode insns in the XScale/iWMMXt space as cp insns
  hw/net/lan9118: Fix RX Status FIFO PEEK value
  hw/net/lan9118: Add symbolic constants for register offsets

Roman Bolshakov (2):
  ui/cocoa: Update path to docs in build tree
  ui/cocoa: Fix openFile: deprecation on Big Sur

Rémi Denis-Courmont (2):
  target/arm: ARMv8.4-TTST extension
  target/arm: enable Small Translation tables in max CPU

 docs/conf.py |  46 ++-
 docs/devel/conf.py   |  15 -
 docs/index.html.in   |  17 -
 docs/interop/conf.py |  28 --
 docs/meson.build |  65 ++--
 docs/specs/conf.py   |  16 -
 docs/system/arm/nuvoton.rst  |   4 +-
 docs/system/conf.py  |  28 --
 docs/tools/conf.py   |  37 --
 docs/user/conf.py|  15 -
 meson.build  |   1 +
 hw/adc/trace.h   |   1 +
 include/hw/adc/npcm7xx_adc.h |  69 
 include/hw/arm/npcm7xx.h |   4 +
 include/hw/misc/npcm7xx_clk.h| 146 ++-
 include/hw/misc/npcm7xx_pwm.h| 105 +
 include/hw/timer/npcm7xx_timer.h |   1 +
 target/arm/cpu.h |  85 -
 hw/adc/npcm7xx_adc.c | 301 +++
 hw/arm/npcm7xx.c |  55 ++-
 hw/arm/npcm7xx_boards.c  |   2 +-
 hw/mem/npcm7xx_mc.c  |   2 +-
 hw/misc/npcm7xx_clk.c| 807 ++-
 hw/misc/npcm7xx_gcr.c|   2 +-
 hw/misc/npcm7xx_pwm.c| 550 ++
 hw/misc/npcm7xx_rng.c|   2 +-
 hw/net/lan9118.c |  26 +-
 hw/nvram/npcm7xx_otp.c   |   2 +-
 hw/ssi/npcm7xx_fiu.c |   2 +-
 hw/timer/npcm7xx_timer.c |  39 +-
 target/arm/cpu64.c   |   1 +
 target/arm/helper.c  |  15 +-
 target/arm/translate.c   |   7 +
 tests/qtest/npcm7xx_adc-test.c   | 377 ++
 tests/qtest/npcm7xx_pwm-test.c   | 490 
 hw/adc/meson.build   |   1 +
 hw/adc/trace-events  |   5 +
 hw/misc/meson.build  |   1 +
 hw/misc/trace-events |   6 +
 tests/qtest/meson.build  |   4 +-
 ui/cocoa.m   |   7 +-
 41 files changed, 3124 insertions(+), 263 deletions(-)
 delete mode 100644 docs/devel/conf.py
 delete mode 100644 docs/index.html.in
 delete mode 100644 docs/interop/conf.py
 delete mode 100644 docs/specs/conf.py
 delete mode 100644 docs/system/conf.py
 delete mode 100644 docs/tools/conf.py
 delete mode 100644 docs/user/conf.py
 create mode 100644 hw/adc/trace.h
 create mode 100644 include/hw/adc/npcm7xx_adc.h
 create mode 100644 include/hw/misc/npcm7xx_pwm.h
 create mode 100644 hw/adc/npcm7xx_adc.c
 create mode 100644 

Re: [Qemu-devel] [PULL 00/21] target-arm queue

[Peter Maydell]

On Tue, 3 Sep 2019 at 16:36, Peter Maydell  wrote:
>
> target-arm queue: this time around is all small fixes
> and changes.
>
> thanks
> -- PMM
>
> The following changes since commit fec105c2abda8567ec15230429c41429b5ee307c:
>
>   Merge remote-tracking branch 
> 'remotes/kraxel/tags/audio-20190828-pull-request' into staging (2019-09-03 
> 14:03:15 +0100)
>
> are available in the Git repository at:
>
>   https://git.linaro.org/people/pmaydell/qemu-arm.git 
> tags/pull-target-arm-20190903
>
> for you to fetch changes up to 5e5584c89f36b302c666bc6db535fd3f7ff35ad2:
>
>   target/arm: Don't abort on M-profile exception return in linux-user mode 
> (2019-09-03 16:20:35 +0100)
>
> 
> target-arm queue:
>  * Revert and correctly fix refactoring of unallocated_encoding()
>  * Take exceptions on ATS instructions when needed
>  * aspeed/timer: Provide back-pressure information for short periods
>  * memory: Remove unused memory_region_iommu_replay_all()
>  * hw/arm/smmuv3: Log a guest error when decoding an invalid STE
>  * hw/arm/smmuv3: Remove spurious error messages on IOVA invalidations
>  * target/arm: Fix SMMLS argument order
>  * hw/arm: Use ARM_CPU_TYPE_NAME() macro when appropriate
>  * hw/arm: Correct reference counting for creation of various objects
>  * includes: remove stale [smp|max]_cpus externs
>  * tcg/README: fix typo
>  * atomic_template: fix indentation in GEN_ATOMIC_HELPER
>  * include/exec/cpu-defs.h: fix typo
>  * target/arm: Free TCG temps in trans_VMOV_64_sp()
>  * target/arm: Don't abort on M-profile exception return in linux-user mode
>
> 


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/4.2
for any user-visible changes.

-- PMM

[Qemu-devel] [PULL 00/21] target-arm queue

[Peter Maydell]

target-arm queue: this time around is all small fixes
and changes.

thanks
-- PMM

The following changes since commit fec105c2abda8567ec15230429c41429b5ee307c:

  Merge remote-tracking branch 
'remotes/kraxel/tags/audio-20190828-pull-request' into staging (2019-09-03 
14:03:15 +0100)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git 
tags/pull-target-arm-20190903

for you to fetch changes up to 5e5584c89f36b302c666bc6db535fd3f7ff35ad2:

  target/arm: Don't abort on M-profile exception return in linux-user mode 
(2019-09-03 16:20:35 +0100)


target-arm queue:
 * Revert and correctly fix refactoring of unallocated_encoding()
 * Take exceptions on ATS instructions when needed
 * aspeed/timer: Provide back-pressure information for short periods
 * memory: Remove unused memory_region_iommu_replay_all()
 * hw/arm/smmuv3: Log a guest error when decoding an invalid STE
 * hw/arm/smmuv3: Remove spurious error messages on IOVA invalidations
 * target/arm: Fix SMMLS argument order
 * hw/arm: Use ARM_CPU_TYPE_NAME() macro when appropriate
 * hw/arm: Correct reference counting for creation of various objects
 * includes: remove stale [smp|max]_cpus externs
 * tcg/README: fix typo
 * atomic_template: fix indentation in GEN_ATOMIC_HELPER
 * include/exec/cpu-defs.h: fix typo
 * target/arm: Free TCG temps in trans_VMOV_64_sp()
 * target/arm: Don't abort on M-profile exception return in linux-user mode


Alex Bennée (2):
  includes: remove stale [smp|max]_cpus externs
  include/exec/cpu-defs.h: fix typo

Andrew Jeffery (1):
  aspeed/timer: Provide back-pressure information for short periods

Emilio G. Cota (2):
  tcg/README: fix typo s/afterwise/afterwards/
  atomic_template: fix indentation in GEN_ATOMIC_HELPER

Eric Auger (3):
  memory: Remove unused memory_region_iommu_replay_all()
  hw/arm/smmuv3: Log a guest error when decoding an invalid STE
  hw/arm/smmuv3: Remove spurious error messages on IOVA invalidations

Peter Maydell (4):
  target/arm: Allow ARMCPRegInfo read/write functions to throw exceptions
  target/arm: Take exceptions on ATS instructions when needed
  target/arm: Free TCG temps in trans_VMOV_64_sp()
  target/arm: Don't abort on M-profile exception return in linux-user mode

Philippe Mathieu-Daudé (6):
  hw/arm: Use ARM_CPU_TYPE_NAME() macro when appropriate
  hw/arm: Use object_initialize_child for correct reference counting
  hw/arm: Use sysbus_init_child_obj for correct reference counting
  hw/arm/fsl-imx: Add the cpu as child of the SoC object
  hw/dma/xilinx_axi: Use object_initialize_child for correct ref. counting
  hw/net/xilinx_axi: Use object_initialize_child for correct ref. counting

Richard Henderson (3):
  Revert "target/arm: Use unallocated_encoding for aarch32"
  target/arm: Factor out unallocated_encoding for aarch32
  target/arm: Fix SMMLS argument order

 accel/tcg/atomic_template.h|   2 +-
 hw/arm/smmuv3-internal.h   |   1 +
 include/exec/cpu-defs.h|   2 +-
 include/exec/memory.h  |  10 
 include/sysemu/sysemu.h|   2 -
 target/arm/cpu.h   |   6 ++-
 target/arm/translate-a64.h |   2 +
 target/arm/translate.h |   2 -
 hw/arm/allwinner-a10.c |   3 +-
 hw/arm/cubieboard.c|   3 +-
 hw/arm/digic.c |   3 +-
 hw/arm/exynos4_boards.c|   4 +-
 hw/arm/fsl-imx25.c |   4 +-
 hw/arm/fsl-imx31.c |   4 +-
 hw/arm/fsl-imx6.c  |   3 +-
 hw/arm/fsl-imx6ul.c|   2 +-
 hw/arm/mcimx7d-sabre.c |   9 ++--
 hw/arm/mps2-tz.c   |  15 +++---
 hw/arm/musca.c |   9 ++--
 hw/arm/smmuv3.c|  18 ---
 hw/arm/xlnx-zynqmp.c   |   8 +--
 hw/dma/xilinx_axidma.c |  16 +++---
 hw/net/xilinx_axienet.c|  17 +++
 hw/timer/aspeed_timer.c|  17 ++-
 memory.c   |   9 
 target/arm/helper.c| 107 +++--
 target/arm/translate-a64.c |  13 +
 target/arm/translate-vfp.inc.c |   2 +
 target/arm/translate.c |  50 +--
 tcg/README |   2 +-
 30 files changed, 244 insertions(+), 101 deletions(-)

Re: [Qemu-devel] [PULL 00/21] target-arm queue

[Peter Maydell]

On Thu, 21 Feb 2019 at 18:57, Peter Maydell  wrote:
>
> Arm queue -- mostly the first slice of my Musca patches.
>
> thanks
> -- PMM
>
> The following changes since commit fc3dbb90f2eb069801bfb4cfe9cbc83cf9c5f4a9:
>
>   Merge remote-tracking branch 'remotes/jnsnow/tags/bitmaps-pull-request' 
> into staging (2019-02-21 13:09:33 +)
>
> are available in the Git repository at:
>
>   https://git.linaro.org/people/pmaydell/qemu-arm.git 
> tags/pull-target-arm-20190221
>
> for you to fetch changes up to 3733f80308d2a7f23f5e39b039e0547aba6c07f1:
>
>   hw/arm/armsse: Make 0x5... alias region work for per-CPU devices 
> (2019-02-21 18:17:48 +)
>
> 
> target-arm queue:
>  * Model the Arm "Musca" development boards: "musca-a" and "musca-b1"
>  * Implement the ARMv8.3-JSConv extension
>  * v8M MPU should use background region as default, not always
>  * Stop unintentional sign extension in pmu_init
>
> 

Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/4.0
for any user-visible changes.

-- PMM

[Qemu-devel] [PULL 00/21] target-arm queue

[Peter Maydell]

Arm queue -- mostly the first slice of my Musca patches.

thanks
-- PMM

The following changes since commit fc3dbb90f2eb069801bfb4cfe9cbc83cf9c5f4a9:

  Merge remote-tracking branch 'remotes/jnsnow/tags/bitmaps-pull-request' into 
staging (2019-02-21 13:09:33 +)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git 
tags/pull-target-arm-20190221

for you to fetch changes up to 3733f80308d2a7f23f5e39b039e0547aba6c07f1:

  hw/arm/armsse: Make 0x5... alias region work for per-CPU devices (2019-02-21 
18:17:48 +)


target-arm queue:
 * Model the Arm "Musca" development boards: "musca-a" and "musca-b1"
 * Implement the ARMv8.3-JSConv extension
 * v8M MPU should use background region as default, not always
 * Stop unintentional sign extension in pmu_init


Aaron Lindsay OS (1):
  target/arm: Stop unintentional sign extension in pmu_init

Peter Maydell (16):
  hw/arm/armsse: Fix memory leak in error-exit path
  target/arm: v8M MPU should use background region as default, not always
  hw/misc/tz-ppc: Support having unused ports in the middle of the range
  hw/timer/pl031: Allow use as an embedded-struct device
  hw/timer/pl031: Convert to using trace events
  hw/char/pl011: Allow use as an embedded-struct device
  hw/char/pl011: Support all interrupt lines
  hw/char/pl011: Use '0x' prefix when logging hex numbers
  hw/arm/armsse: Document SRAM_ADDR_WIDTH property in header comment
  hw/arm/armsse: Allow boards to specify init-svtor
  hw/arm/musca.c: Implement models of the Musca-A and -B1 boards
  hw/arm/musca: Add PPCs
  hw/arm/musca: Add MPCs
  hw/arm/musca: Wire up PL031 RTC
  hw/arm/musca: Wire up PL011 UARTs
  hw/arm/armsse: Make 0x5... alias region work for per-CPU devices

Richard Henderson (4):
  target/arm: Restructure disas_fp_int_conv
  target/arm: Split out vfp_helper.c
  target/arm: Rearrange Floating-point data-processing (2 regs)
  target/arm: Implement ARMv8.3-JSConv

 hw/arm/Makefile.objs|1 +
 target/arm/Makefile.objs|2 +-
 include/hw/arm/armsse.h |7 +-
 include/hw/char/pl011.h |   34 ++
 include/hw/misc/tz-ppc.h|8 +-
 include/hw/timer/pl031.h|   44 ++
 target/arm/cpu.h|   10 +
 target/arm/helper.h |3 +
 hw/arm/armsse.c |   44 +-
 hw/arm/musca.c  |  669 ++
 hw/char/pl011.c |   81 +--
 hw/misc/tz-ppc.c|   32 ++
 hw/timer/pl031.c|   80 ++-
 target/arm/cpu.c|1 +
 target/arm/cpu64.c  |2 +
 target/arm/helper.c | 1072 +--
 target/arm/translate-a64.c  |  120 ++--
 target/arm/translate.c  |  237 
 target/arm/vfp_helper.c | 1176 +++
 MAINTAINERS |7 +
 default-configs/arm-softmmu.mak |1 +
 hw/timer/trace-events   |6 +
 22 files changed, 2307 insertions(+), 1330 deletions(-)
 create mode 100644 include/hw/timer/pl031.h
 create mode 100644 hw/arm/musca.c
 create mode 100644 target/arm/vfp_helper.c

[Qemu-devel] [PULL 00/21] target-arm queue

[Peter Maydell]

target-arm queue of various easier things that had piled
up while I was on holiday.

thanks
-- PMM

The following changes since commit 506e4a00de01e0b29fa83db5cbbc3d154253b4ea:

  Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-3.1-20180925' into 
staging (2018-09-25 13:30:45 +0100)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git 
tags/pull-target-arm-20180925

for you to fetch changes up to 4a87106b160a3e72152443065fb92f8a1313c23d:

  target/arm: Start AArch32 CPUs with EL2 but not EL3 in Hyp mode (2018-09-25 
14:14:07 +0100)


target-arm queue:
 * target/arm: Fix cpu_get_tb_cpu_state() for non-SVE CPUs
 * hw/arm/exynos4210: fix Exynos4210 UART support
 * hw/arm/virt-acpi-build: Add a check for memory-less NUMA nodes
 * arm: Add BBC micro:bit machine
 * aspeed/i2c: Fix interrupt handling bugs
 * hw/arm/smmu-common: Fix the name of the iommu memory regions
 * hw/arm/smmuv3: fix eventq recording and IRQ triggerring
 * hw/intc/arm_gic: Document QEMU interface
 * hw/intc/arm_gic: Drop GIC_BASE_IRQ macro
 * hw/net/pcnet-pci: Convert away from old_mmio accessors
 * hw/timer/cmsdk-apb-dualtimer: Add missing 'break' statements
 * aspeed/timer: fix compile breakage with clang 3.4.2
 * hw/arm/aspeed: change the FMC flash model of the AST2500 evb
 * hw/arm/aspeed: Minor code cleanups
 * target/arm: Start AArch32 CPUs with EL2 but not EL3 in Hyp mode


Bartlomiej Zolnierkiewicz (1):
  hw/arm/exynos4210: fix Exynos4210 UART support

Cédric Le Goater (5):
  aspeed/i2c: interrupts should be cleared by software only
  aspeed/timer: fix compile breakage with clang 3.4.2
  hw/arm/aspeed: change the FMC flash model of the AST2500 evb
  hw/arm/aspeed: Add an Aspeed machine class
  aspeed/smc: fix some alignment issues

Eric Auger (2):
  hw/arm/smmu-common: Fix the name of the iommu memory regions
  hw/arm/smmuv3: fix eventq recording and IRQ triggerring

Guenter Roeck (2):
  aspeed/i2c: Handle receive command in separate function
  aspeed/i2c: Fix receive done interrupt handling

Joel Stanley (3):
  MAINTAINERS: Add NRF51 entry
  arm: Add Nordic Semiconductor nRF51 SoC
  arm: Add BBC micro:bit machine

Peter Maydell (6):
  hw/intc/arm_gic: Document QEMU interface
  hw/intc/arm_gic: Drop GIC_BASE_IRQ macro
  hw/net/pcnet-pci: Convert away from old_mmio accessors
  hw/net/pcnet-pci: Unify pcnet_ioport_read/write and pcnet_mmio_read/write
  hw/timer/cmsdk-apb-dualtimer: Add missing 'break' statements
  target/arm: Start AArch32 CPUs with EL2 but not EL3 in Hyp mode

Richard Henderson (1):
  target/arm: Fix cpu_get_tb_cpu_state() for non-SVE CPUs

Shannon Zhao (1):
  hw/arm/virt-acpi-build: Add a check for memory-less NUMA nodes

 hw/arm/Makefile.objs|   1 +
 hw/arm/smmuv3-internal.h|  26 ++---
 hw/intc/gic_internal.h  |   2 -
 include/hw/arm/aspeed.h |  46 +
 include/hw/arm/nrf51_soc.h  |  41 
 include/hw/intc/arm_gic.h   |  43 
 include/hw/timer/aspeed_timer.h |   3 +-
 hw/arm/aspeed.c | 212 +---
 hw/arm/exynos4210.c |   8 +-
 hw/arm/microbit.c   |  67 +
 hw/arm/nrf51_soc.c  | 133 +
 hw/arm/smmu-common.c|   6 +-
 hw/arm/smmuv3.c |   2 +-
 hw/arm/virt-acpi-build.c|  10 +-
 hw/i2c/aspeed_i2c.c |  63 
 hw/intc/arm_gic.c   |  31 +++---
 hw/intc/arm_gic_common.c|   1 -
 hw/net/pcnet-pci.c  |  98 ++-
 hw/ssi/aspeed_smc.c |   8 +-
 hw/timer/aspeed_timer.c |   1 -
 hw/timer/cmsdk-apb-dualtimer.c  |   2 +
 target/arm/cpu.c|  14 ++-
 target/arm/helper.c |  45 +
 MAINTAINERS |   8 ++
 default-configs/arm-softmmu.mak |   1 +
 hw/net/trace-events |   6 --
 26 files changed, 542 insertions(+), 336 deletions(-)
 create mode 100644 include/hw/arm/aspeed.h
 create mode 100644 include/hw/arm/nrf51_soc.h
 create mode 100644 hw/arm/microbit.c
 create mode 100644 hw/arm/nrf51_soc.c

Re: [Qemu-devel] [PULL 00/21] target-arm queue

[Peter Maydell]

On 10 May 2018 at 18:44, Peter Maydell  wrote:
> The following changes since commit e5cd695266c5709308aa95b1baae499e4b5d4544:
>
>   Merge remote-tracking branch 'remotes/cody/tags/block-pull-request' into 
> staging (2018-05-08 17:05:58 +0100)
>
> are available in the Git repository at:
>
>   git://git.linaro.org/people/pmaydell/qemu-arm.git 
> tags/pull-target-arm-20180510
>
> for you to fetch changes up to 9a9f1f59521f46e8ff4527d9a2b52f83577e2aa3:
>
>   target/arm: Clear SVE high bits for FMOV (2018-05-10 18:10:58 +0100)
>
> 
> target-arm queue:
>  * hw/arm/iotkit.c: fix minor memory leak
>  * softfloat: fix wrong-exception-flags bug for multiply-add corner case
>  * arm: isolate and clean up DTB generation
>  * implement Arm v8.1-Atomics extension
>  * Fix some bugs and missing instructions in the v8.2-FP16 extension
>

Applied, thanks.

-- PMM

Re: [Qemu-devel] [PULL 00/21] target-arm queue

[no-reply]

Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 20180510174519.11264-1-peter.mayd...@linaro.org
Subject: [Qemu-devel] [PULL 00/21] target-arm queue

=== TEST SCRIPT BEGIN ===
#!/bin/bash

BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0

git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram

commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
echo "Checking PATCH $n/$total: $(git log -n 1 --format=%s $c)..."
if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
failed=1
echo
fi
n=$((n+1))
done

exit $failed
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 t [tag update]
patchew/20180502221552.3873-1-richard.hender...@linaro.org -> 
patchew/20180502221552.3873-1-richard.hender...@linaro.org
 t [tag update]
patchew/20180503115620.10596-1-edgar.igles...@gmail.com -> 
patchew/20180503115620.10596-1-edgar.igles...@gmail.com
 t [tag update]patchew/20180509165530.29561-1-mre...@redhat.com -> 
patchew/20180509165530.29561-1-mre...@redhat.com
 t [tag update]
patchew/20180510094206.15354-1-alex.ben...@linaro.org -> 
patchew/20180510094206.15354-1-alex.ben...@linaro.org
 t [tag update]
patchew/20180510140141.12120-1-peter.mayd...@linaro.org -> 
patchew/20180510140141.12120-1-peter.mayd...@linaro.org
 t [tag update]
patchew/20180510140934.22855-1-peter.mayd...@linaro.org -> 
patchew/20180510140934.22855-1-peter.mayd...@linaro.org
 t [tag update]
patchew/20180510143618.23673-1-peter.mayd...@linaro.org -> 
patchew/20180510143618.23673-1-peter.mayd...@linaro.org
 * [new tag]   
patchew/20180510174519.11264-1-peter.mayd...@linaro.org -> 
patchew/20180510174519.11264-1-peter.mayd...@linaro.org
Auto packing the repository in background for optimum performance.
See "git help gc" for manual housekeeping.
Switched to a new branch 'test'
ccdba81c4b target/arm: Clear SVE high bits for FMOV
64003f64f0 target/arm: Fix float16 to/from int16
600be1201a target/arm: Implement vector shifted FCVT for fp16
0f941356c9 target/arm: Implement vector shifted SCVF/UCVF for fp16
3ded533d22 target/arm: Enable ARM_FEATURE_V8_ATOMICS for user-only
9d58b9b45c target/arm: Implement CAS and CASP
51a26a9014 target/arm: Fill in disas_ldst_atomic
de4ccb142c target/arm: Introduce ARM_FEATURE_V8_ATOMICS and initial decode
3b7e02239c target/riscv: Use new atomic min/max expanders
d8820204cf tcg: Use GEN_ATOMIC_HELPER_FN for opposite endian atomic add
587522510f tcg: Introduce atomic helpers for integer min/max
adbe86c2cb target/xtensa: Use new min/max expanders
9f9ed0f8b4 target/arm: Use new min/max expanders
0386c2a4f5 tcg: Introduce helpers for integer min/max
7a13cbc1df atomic.h: Work around gcc spurious "unused value" warning
704fd2643a make sure that we aren't overwriting mc->get_hotplug_handler by 
accident
e35977cfc3 arm/boot: split load_dtb() from arm_load_kernel()
b46a5f4740 platform-bus-device: use device plug callback instead of 
machine_done notifier
318eae8151 pc: simplify MachineClass::get_hotplug_handler handling
d99828cef6 softfloat: Handle default NaN mode after pickNaNMulAdd, not before
058260b178 hw/arm/iotkit.c: fix minor memory leak

=== OUTPUT BEGIN ===
Checking PATCH 1/21: hw/arm/iotkit.c: fix minor memory leak...
Checking PATCH 2/21: softfloat: Handle default NaN mode after pickNaNMulAdd, 
not before...
Checking PATCH 3/21: pc: simplify MachineClass::get_hotplug_handler handling...
Checking PATCH 4/21: platform-bus-device: use device plug callback instead of 
machine_done notifier...
Checking PATCH 5/21: arm/boot: split load_dtb() from arm_load_kernel()...
Checking PATCH 6/21: make sure that we aren't overwriting 
mc->get_hotplug_handler by accident...
Checking PATCH 7/21: atomic.h: Work around gcc spurious "unused value" 
warning...
Checking PATCH 8/21: tcg: Introduce helpers for integer min/max...
Checking PATCH 9/21: target/arm: Use new min/max expanders...
Checking PATCH 10/21: target/xtensa: Use new min/max expanders...
Checking PATCH 11/21: tcg: Introduce atomic helpers for integer min/max...
ERROR: memory barrier without comment
#58: FILE: accel/tcg/atomic_template.h:137:
+smp_mb();   \

ERROR: memory barrier without comment
#98: FILE: accel/tcg/atomic_template.h:285:
+smp_mb();   \

total: 2 errors, 0 warnings, 236 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 12/21: tcg: Use GEN_ATOMIC_HELPER_FN for oppos

[Qemu-devel] [PULL 00/21] target-arm queue

[Peter Maydell]

The following changes since commit e5cd695266c5709308aa95b1baae499e4b5d4544:

  Merge remote-tracking branch 'remotes/cody/tags/block-pull-request' into 
staging (2018-05-08 17:05:58 +0100)

are available in the Git repository at:

  git://git.linaro.org/people/pmaydell/qemu-arm.git 
tags/pull-target-arm-20180510

for you to fetch changes up to 9a9f1f59521f46e8ff4527d9a2b52f83577e2aa3:

  target/arm: Clear SVE high bits for FMOV (2018-05-10 18:10:58 +0100)


target-arm queue:
 * hw/arm/iotkit.c: fix minor memory leak
 * softfloat: fix wrong-exception-flags bug for multiply-add corner case
 * arm: isolate and clean up DTB generation
 * implement Arm v8.1-Atomics extension
 * Fix some bugs and missing instructions in the v8.2-FP16 extension


Igor Mammedov (4):
  pc: simplify MachineClass::get_hotplug_handler handling
  platform-bus-device: use device plug callback instead of machine_done 
notifier
  arm/boot: split load_dtb() from arm_load_kernel()
  make sure that we aren't overwriting mc->get_hotplug_handler by accident

Peter Maydell (3):
  hw/arm/iotkit.c: fix minor memory leak
  softfloat: Handle default NaN mode after pickNaNMulAdd, not before
  atomic.h: Work around gcc spurious "unused value" warning

Richard Henderson (14):
  tcg: Introduce helpers for integer min/max
  target/arm: Use new min/max expanders
  target/xtensa: Use new min/max expanders
  tcg: Introduce atomic helpers for integer min/max
  tcg: Use GEN_ATOMIC_HELPER_FN for opposite endian atomic add
  target/riscv: Use new atomic min/max expanders
  target/arm: Introduce ARM_FEATURE_V8_ATOMICS and initial decode
  target/arm: Fill in disas_ldst_atomic
  target/arm: Implement CAS and CASP
  target/arm: Enable ARM_FEATURE_V8_ATOMICS for user-only
  target/arm: Implement vector shifted SCVF/UCVF for fp16
  target/arm: Implement vector shifted FCVT for fp16
  target/arm: Fix float16 to/from int16
  target/arm: Clear SVE high bits for FMOV

 accel/tcg/atomic_template.h | 112 ++
 accel/tcg/tcg-runtime.h |   8 +
 hw/ppc/e500.h   |   5 +
 include/hw/arm/arm.h|  45 +++-
 include/hw/arm/sysbus-fdt.h |  37 +---
 include/hw/arm/virt.h   |   1 +
 include/hw/i386/pc.h|   8 -
 include/hw/platform-bus.h   |   4 +-
 include/qemu/atomic.h   |   2 +-
 target/arm/cpu.h|   1 +
 target/arm/helper-a64.h |   2 +
 target/arm/helper.h |   4 +-
 tcg/tcg-op.h|  50 +
 tcg/tcg.h   |   8 +
 fpu/softfloat.c |  52 +++--
 hw/arm/boot.c   |  72 ++-
 hw/arm/iotkit.c |   1 +
 hw/arm/sysbus-fdt.c |  64 +-
 hw/arm/virt.c   |  96 ++---
 hw/core/platform-bus.c  |  29 +--
 hw/i386/pc.c|   7 +-
 hw/ppc/e500.c   |  38 ++--
 hw/ppc/e500plat.c   |  32 +++
 hw/ppc/spapr.c  |   1 +
 hw/s390x/s390-virtio-ccw.c  |   1 +
 linux-user/elfload.c|   1 +
 target/arm/cpu64.c  |   1 +
 target/arm/helper-a64.c |  43 
 target/arm/helper.c |  53 -
 target/arm/translate-a64.c  | 490 +---
 target/riscv/translate.c|  72 ++-
 target/xtensa/translate.c   |  50 +++--
 tcg/tcg-op.c|  48 +
 33 files changed, 934 insertions(+), 504 deletions(-)

[Qemu-devel] [PULL 00/21] target-arm queue

[Peter Maydell]

target-arm queue: mostly just cleanup/minor stuff, but this does
include the raspi3 board model.

-- PMM

The following changes since commit 9f9c53368b219a9115eddb39f0ff5ad19c977134:

  Merge remote-tracking branch 'remotes/vivier/tags/m68k-for-2.12-pull-request' 
into staging (2018-02-15 10:14:11 +)

are available in the Git repository at:

  git://git.linaro.org/people/pmaydell/qemu-arm.git 
tags/pull-target-arm-20180215

for you to fetch changes up to e545f0f9be1f9e60951017c1e6558216732cc14e:

  target/arm: Implement v8M MSPLIM and PSPLIM registers (2018-02-15 13:48:11 
+)


target-arm queue:
 * aspeed: code cleanup to use unimplemented_device
 * add 'raspi3' RaspberryPi 3 machine model
 * more SVE prep work
 * v8M: add minor missing registers
 * v7M: fix bug where we weren't migrating v7m.other_sp
 * v7M: fix bugs in handling of interrupt registers for
   external interrupts beyond 32


Pekka Enberg (3):
  bcm2836: Make CPU type configurable
  raspi: Raspberry Pi 3 support
  raspi: Add "raspi3" machine type

Peter Maydell (11):
  hw/intc/armv7m_nvic: Don't hardcode M profile ID registers in NVIC
  hw/intc/armv7m_nvic: Fix ICSR PENDNMISET/CLR handling
  hw/intc/armv7m_nvic: Implement M profile cache maintenance ops
  hw/intc/armv7m_nvic: Implement v8M CPPWR register
  hw/intc/armv7m_nvic: Implement cache ID registers
  hw/intc/armv7m_nvic: Implement SCR
  target/arm: Implement writing to CONTROL_NS for v8M
  hw/intc/armv7m_nvic: Fix byte-to-interrupt number conversions
  target/arm: Add AIRCR to vmstate struct
  target/arm: Migrate v7m.other_sp
  target/arm: Implement v8M MSPLIM and PSPLIM registers

Philippe Mathieu-Daudé (2):
  hw/arm/aspeed: directly map the serial device to the system address space
  hw/arm/aspeed: simplify using the 'unimplemented device' for aspeed_soc.io

Richard Henderson (5):
  target/arm: Remove ARM_CP_64BIT from ZCR_EL registers
  target/arm: Enforce FP access to FPCR/FPSR
  target/arm: Suppress TB end for FPCR/FPSR
  target/arm: Enforce access to ZCR_EL at translation
  target/arm: Handle SVE registers when using clear_vec_high

 include/hw/arm/aspeed_soc.h |   1 -
 include/hw/arm/bcm2836.h|   1 +
 target/arm/cpu.h|  71 -
 target/arm/internals.h  |   6 ++
 hw/arm/aspeed_soc.c |  35 ++---
 hw/arm/bcm2836.c|  17 +++--
 hw/arm/raspi.c  |  57 +++---
 hw/intc/armv7m_nvic.c   |  98 ++--
 target/arm/cpu.c|  28 +++
 target/arm/helper.c |  84 +++-
 target/arm/machine.c|  84 
 target/arm/translate-a64.c  | 181 
 12 files changed, 452 insertions(+), 211 deletions(-)

Re: [Qemu-devel] [PULL 00/21] target-arm queue

[Peter Maydell]

On 25 January 2018 at 13:43, Peter Maydell  wrote:
>
> Arm queue built up to a point where it seems worth sending:
> various bug fixes, plus RTH's refactoring in preparation for SVE.
>
> thanks
> -- PMM
>
>
> The following changes since commit 0f79bfe38a2cf0f43c7ea4959da7f8ebd7858f3d:
>
>   Merge remote-tracking branch 
> 'remotes/vivier2/tags/linux-user-for-2.12-pull-request' into staging 
> (2018-01-25 09:53:53 +)
>
> are available in the git repository at:
>
>   git://git.linaro.org/people/pmaydell/qemu-arm.git 
> tags/pull-target-arm-20180125
>
> for you to fetch changes up to 24da047af0e99a83fcc0d50b86c0f2627f7418b3:
>
>   pl110: Implement vertical compare/next base interrupts (2018-01-25 11:45:30 
> +)
>
> 
> target-arm queue:
>  * target/arm: Fix address truncation in 64-bit pagetable walks
>  * i.MX: Fix FEC/ENET receive functions
>  * target/arm: preparatory refactoring for SVE emulation
>  * hw/intc/arm_gic: Prevent the GIC from signaling an IRQ when it's "active 
> and pending"
>  * hw/intc/arm_gic: Fix C_RPR value on idle priority
>  * hw/intc/arm_gic: Fix group priority computation for group 1 IRQs
>  * hw/intc/arm_gic: Fix the NS view of C_BPR when C_CTRL.CBPR is 1
>  * hw/arm/virt: Check that the CPU realize method succeeded
>  * sdhci: fix a NULL pointer dereference due to uninitialized AddressSpace 
> object
>  * xilinx_spips: Correct usage of an uninitialized local variable
>  * pl110: Implement vertical compare/next base interrupts
>

Applied, thanks.

-- PMM

Re: [Qemu-devel] [PULL 00/21] target-arm queue

[no-reply]

Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 1516887809-6265-1-git-send-email-peter.mayd...@linaro.org
Subject: [Qemu-devel] [PULL 00/21] target-arm queue

=== TEST SCRIPT BEGIN ===
#!/bin/bash

BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0

git config --local diff.renamelimit 0
git config --local diff.renames True

commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
echo "Checking PATCH $n/$total: $(git log -n 1 --format=%s $c)..."
if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
failed=1
echo
fi
n=$((n+1))
done

exit $failed
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 * [new tag]   
patchew/1516887809-6265-1-git-send-email-peter.mayd...@linaro.org -> 
patchew/1516887809-6265-1-git-send-email-peter.mayd...@linaro.org
Switched to a new branch 'test'
a7ead1ca00 pl110: Implement vertical compare/next base interrupts
f66ce5c2c3 xilinx_spips: Correct usage of an uninitialized local variable
d88421481d sdhci: fix a NULL pointer dereference due to uninitialized 
AddresSpace object
7564bd6dfb hw/arm/virt: Check that the CPU realize method succeeded
18db7a35b4 hw/intc/arm_gic: Fix the NS view of C_BPR when C_CTRL.CBPR is 1
157a918a47 hw/intc/arm_gic: Fix group priority computation for group 1 IRQs
a896e5197e hw/intc/arm_gic: Fix C_RPR value on idle priority
ed702de6c2 hw/intc/arm_gic: Prevent the GIC from signaling an IRQ when it's 
"active and pending"
0c5df69251 target/arm: Simplify fp_exception_el for user-only
0901e742d2 target/arm: Hoist store to flags output in cpu_get_tb_cpu_state
30d076c766 target/arm: Move cpu_get_tb_cpu_state out of line
9bc4918ade target/arm: Add ARM_FEATURE_SVE
9afce6e002 vmstate: Add VMSTATE_UINT64_SUB_ARRAY
911f6046fd target/arm: Add aa{32, 64}_vfp_{dreg, qreg} helpers
768420eeb2 target/arm: Change the type of vfp.regs
d2beafabf0 target/arm: Use pointers in neon tbl helper
e00821354c target/arm: Use pointers in neon zip/uzp helpers
ac24cb1f18 target/arm: Use pointers in crypto helpers
df207ebf53 target/arm: Mark disas_set_insn_syndrome inline
a13bffeacc i.MX: Fix FEC/ENET receive funtions
cc82dfe8c8 target/arm: Fix 32-bit address truncation

=== OUTPUT BEGIN ===
Checking PATCH 1/21: target/arm: Fix 32-bit address truncation...
Checking PATCH 2/21: i.MX: Fix FEC/ENET receive funtions...
Checking PATCH 3/21: target/arm: Mark disas_set_insn_syndrome inline...
Checking PATCH 4/21: target/arm: Use pointers in crypto helpers...
Checking PATCH 5/21: target/arm: Use pointers in neon zip/uzp helpers...
ERROR: trailing whitespace
#321: FILE: target/arm/translate.c:4691:
+$

total: 1 errors, 0 warnings, 373 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 6/21: target/arm: Use pointers in neon tbl helper...
Checking PATCH 7/21: target/arm: Change the type of vfp.regs...
Checking PATCH 8/21: target/arm: Add aa{32, 64}_vfp_{dreg, qreg} helpers...
ERROR: spaces required around that '*' (ctx:VxV)
#88: FILE: target/arm/arch_dump.c:104:
+note.vfp.vregs[2*i + 0] = cpu_to_dump64(s, q[0]);
 ^

ERROR: spaces required around that '*' (ctx:VxV)
#89: FILE: target/arm/arch_dump.c:105:
+note.vfp.vregs[2*i + 1] = cpu_to_dump64(s, q[1]);
 ^

total: 2 errors, 0 warnings, 327 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 9/21: vmstate: Add VMSTATE_UINT64_SUB_ARRAY...
Checking PATCH 10/21: target/arm: Add ARM_FEATURE_SVE...
Checking PATCH 11/21: target/arm: Move cpu_get_tb_cpu_state out of line...
Checking PATCH 12/21: target/arm: Hoist store to flags output in 
cpu_get_tb_cpu_state...
Checking PATCH 13/21: target/arm: Simplify fp_exception_el for user-only...
Checking PATCH 14/21: hw/intc/arm_gic: Prevent the GIC from signaling an IRQ 
when it's "active and pending"...
Checking PATCH 15/21: hw/intc/arm_gic: Fix C_RPR value on idle priority...
Checking PATCH 16/21: hw/intc/arm_gic: Fix group priority computation for group 
1 IRQs...
Checking PATCH 17/21: hw/intc/arm_gic: Fix the NS view of C_BPR when 
C_CTRL.CBPR is 1...
Checking PATCH 18/21: hw/arm/virt: Check that the CPU realize method 
succeeded...
Checking PATCH 19/21: sdhci: fix a NULL pointer dereference due to 
uninitialized AddresSpace object...
Checking PATCH 20/21: xilinx_spips: Correct usage of an uninitialized local 
variable...
Checking PATCH 21/21: pl110: Implement vertical compare/next base interrupts...
=== OUTPUT END ===

Test command exited with code: 1


---
Email generated automatically by Patchew [http

[Qemu-devel] [PULL 00/21] target-arm queue

[Peter Maydell]

Arm queue built up to a point where it seems worth sending:
various bug fixes, plus RTH's refactoring in preparation for SVE.

thanks
-- PMM
 
 
The following changes since commit 0f79bfe38a2cf0f43c7ea4959da7f8ebd7858f3d:

  Merge remote-tracking branch 
'remotes/vivier2/tags/linux-user-for-2.12-pull-request' into staging 
(2018-01-25 09:53:53 +)

are available in the git repository at:

  git://git.linaro.org/people/pmaydell/qemu-arm.git 
tags/pull-target-arm-20180125

for you to fetch changes up to 24da047af0e99a83fcc0d50b86c0f2627f7418b3:

  pl110: Implement vertical compare/next base interrupts (2018-01-25 11:45:30 
+)


target-arm queue:
 * target/arm: Fix address truncation in 64-bit pagetable walks
 * i.MX: Fix FEC/ENET receive functions
 * target/arm: preparatory refactoring for SVE emulation
 * hw/intc/arm_gic: Prevent the GIC from signaling an IRQ when it's "active and 
pending"
 * hw/intc/arm_gic: Fix C_RPR value on idle priority
 * hw/intc/arm_gic: Fix group priority computation for group 1 IRQs
 * hw/intc/arm_gic: Fix the NS view of C_BPR when C_CTRL.CBPR is 1
 * hw/arm/virt: Check that the CPU realize method succeeded
 * sdhci: fix a NULL pointer dereference due to uninitialized AddressSpace 
object
 * xilinx_spips: Correct usage of an uninitialized local variable
 * pl110: Implement vertical compare/next base interrupts


Ard Biesheuvel (1):
  target/arm: Fix 32-bit address truncation

Francisco Iglesias (1):
  xilinx_spips: Correct usage of an uninitialized local variable

Jean-Christophe Dubois (1):
  i.MX: Fix FEC/ENET receive funtions

Linus Walleij (1):
  pl110: Implement vertical compare/next base interrupts

Luc MICHEL (4):
  hw/intc/arm_gic: Prevent the GIC from signaling an IRQ when it's "active 
and pending"
  hw/intc/arm_gic: Fix C_RPR value on idle priority
  hw/intc/arm_gic: Fix group priority computation for group 1 IRQs
  hw/intc/arm_gic: Fix the NS view of C_BPR when C_CTRL.CBPR is 1

Peter Maydell (1):
  hw/arm/virt: Check that the CPU realize method succeeded

Philippe Mathieu-Daudé (1):
  sdhci: fix a NULL pointer dereference due to uninitialized AddresSpace 
object

Richard Henderson (11):
  target/arm: Mark disas_set_insn_syndrome inline
  target/arm: Use pointers in crypto helpers
  target/arm: Use pointers in neon zip/uzp helpers
  target/arm: Use pointers in neon tbl helper
  target/arm: Change the type of vfp.regs
  target/arm: Add aa{32, 64}_vfp_{dreg, qreg} helpers
  vmstate: Add VMSTATE_UINT64_SUB_ARRAY
  target/arm: Add ARM_FEATURE_SVE
  target/arm: Move cpu_get_tb_cpu_state out of line
  target/arm: Hoist store to flags output in cpu_get_tb_cpu_state
  target/arm: Simplify fp_exception_el for user-only

 include/hw/sd/sdhci.h   |   1 +
 include/migration/vmstate.h |   9 ++-
 target/arm/cpu.h| 157 -
 target/arm/helper.h |  46 +--
 target/arm/translate.h  |   2 +-
 hw/arm/virt.c   |   2 +-
 hw/display/pl110.c  |  30 +++-
 hw/intc/arm_gic.c   |  25 +-
 hw/net/imx_fec.c|   8 +-
 hw/sd/sdhci.c   |   1 +
 hw/ssi/xilinx_spips.c   |  18 -
 linux-user/signal.c |  22 +++---
 target/arm/arch_dump.c  |   8 +-
 target/arm/crypto_helper.c  | 184 +---
 target/arm/helper-a64.c |   5 +-
 target/arm/helper.c | 164 +++
 target/arm/kvm32.c  |   4 +-
 target/arm/kvm64.c  |  31 +++-
 target/arm/machine.c|   2 +-
 target/arm/neon_helper.c| 162 --
 target/arm/op_helper.c  |  17 ++--
 target/arm/translate-a64.c  | 100 
 target/arm/translate.c  | 134 +---
 23 files changed, 607 insertions(+), 525 deletions(-)

Re: [Qemu-devel] [PULL 00/21] target-arm queue

[Peter Maydell]

On 28 February 2017 at 17:15, Peter Maydell  wrote:
> Second lot of ARM changes to sneak in before freeze:
>  * fixed version of the raspi2 sd controller patches
>  * GICv3 save/restore
>  * v7M QOMify
>
> I've also included the Linux header update patches stolen
> from Paolo's pullreq since it hasn't quite hit master yet.
>
> thanks
> -- PMM
>
> The following changes since commit 1bbe5dc66b770d7bedd1d51d7935da948a510dd6:
>
>   Merge remote-tracking branch 
> 'remotes/pmaydell/tags/pull-target-arm-20170228' into staging (2017-02-28 
> 14:50:17 +)
>
> are available in the git repository at:
>
>   git://git.linaro.org/people/pmaydell/qemu-arm.git 
> tags/pull-target-arm-20170228-1
>
> for you to fetch changes up to 1eeb5c7deacbfb4d4cad17590a16a99f3d85eabb:
>
>   bcm2835: add sdhost and gpio controllers (2017-02-28 17:10:00 +)
>
> 
> target-arm queue:
>  * raspi2: add gpio controller and sdhost controller, with
>the wiring so the guest can switch which controller the
>SD card is attached to
>(this is sufficient to get raspbian kernels to boot)
>  * GICv3: support state save/restore from KVM
>  * update Linux headers to 4.11
>  * refactor and QOMify the ARMv7M container object

Applied, thanks.

-- PMM

[Qemu-devel] [PULL 00/21] target-arm queue

[Peter Maydell]

Second lot of ARM changes to sneak in before freeze:
 * fixed version of the raspi2 sd controller patches
 * GICv3 save/restore
 * v7M QOMify

I've also included the Linux header update patches stolen
from Paolo's pullreq since it hasn't quite hit master yet.

thanks
-- PMM

The following changes since commit 1bbe5dc66b770d7bedd1d51d7935da948a510dd6:

  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20170228' 
into staging (2017-02-28 14:50:17 +)

are available in the git repository at:

  git://git.linaro.org/people/pmaydell/qemu-arm.git 
tags/pull-target-arm-20170228-1

for you to fetch changes up to 1eeb5c7deacbfb4d4cad17590a16a99f3d85eabb:

  bcm2835: add sdhost and gpio controllers (2017-02-28 17:10:00 +)


target-arm queue:
 * raspi2: add gpio controller and sdhost controller, with
   the wiring so the guest can switch which controller the
   SD card is attached to
   (this is sufficient to get raspbian kernels to boot)
 * GICv3: support state save/restore from KVM
 * update Linux headers to 4.11
 * refactor and QOMify the ARMv7M container object


Clement Deschamps (3):
  hw/sd: add card-reparenting function
  bcm2835_gpio: add bcm2835 gpio controller
  bcm2835: add sdhost and gpio controllers

Paolo Bonzini (2):
  update-linux-headers: update for 4.11
  update Linux headers to 4.11

Peter Maydell (12):
  armv7m: Abstract out the "load kernel" code
  armv7m: Move NVICState struct definition into header
  armv7m: QOMify the armv7m container
  armv7m: Use QOMified armv7m object in armv7m_init()
  armv7m: Make ARMv7M object take memory region link
  armv7m: Make NVIC expose a memory region rather than mapping itself
  armv7m: Make bitband device take the address space to access
  armv7m: Don't put core v7M devices under CONFIG_STELLARIS
  armv7m: Split systick out from NVIC
  stm32f205: Create armv7m object without using armv7m_init()
  stm32f205: Rename 'nvic' local to 'armv7m'
  qdev: Have qdev_set_parent_bus() handle devices already on a bus

Vijaya Kumar K (4):
  hw/intc/arm_gicv3_kvm: Add ICC_SRE_EL1 register to vmstate
  hw/intc/arm_gicv3_kvm: Implement get/put functions
  target-arm: Add GICv3CPUState in CPUARMState struct
  hw/intc/arm_gicv3_kvm: Reset GICv3 cpu interface registers

 hw/gpio/Makefile.objs  |   1 +
 hw/intc/Makefile.objs  |   2 +-
 hw/timer/Makefile.objs |   1 +
 hw/intc/gicv3_internal.h   |   3 +
 include/hw/arm/arm.h   |  12 +
 include/hw/arm/armv7m.h|  63 +++
 include/hw/arm/armv7m_nvic.h   |  62 ++
 include/hw/arm/bcm2835_peripherals.h   |   4 +
 include/hw/arm/stm32f205_soc.h |   4 +-
 include/hw/gpio/bcm2835_gpio.h |  39 ++
 include/hw/intc/arm_gicv3_common.h |   1 +
 include/hw/sd/sd.h |  11 +
 include/hw/timer/armv7m_systick.h  |  34 ++
 include/standard-headers/asm-x86/hyperv.h  |   8 +
 include/standard-headers/linux/input-event-codes.h |   2 +-
 include/standard-headers/linux/pci_regs.h  |  25 +
 include/standard-headers/linux/virtio_ids.h|   1 +
 linux-headers/asm-arm/kvm.h|  15 +
 linux-headers/asm-arm/unistd-common.h  | 357 
 linux-headers/asm-arm/unistd-eabi.h|   5 +
 linux-headers/asm-arm/unistd-oabi.h|  17 +
 linux-headers/asm-arm/unistd.h | 419 +-
 linux-headers/asm-arm64/kvm.h  |  13 +
 linux-headers/asm-powerpc/kvm.h|  27 +
 linux-headers/asm-powerpc/unistd.h |   1 +
 linux-headers/asm-x86/kvm_para.h   |  13 +-
 linux-headers/linux/kvm.h  |  24 +-
 linux-headers/linux/kvm_para.h |   2 +
 linux-headers/linux/userfaultfd.h  |  67 ++-
 linux-headers/linux/vfio.h |  10 +
 target/arm/cpu.h   |   2 +
 hw/arm/armv7m.c| 379 -
 hw/arm/bcm2835_peripherals.c   |  43 +-
 hw/arm/netduino2.c |   7 +-
 hw/arm/stm32f205_soc.c |  28 +-
 hw/core/qdev.c |  14 +
 hw/gpio/bcm2835_gpio.c | 353 
 hw/intc/arm_gicv3_common.c |  38 ++
 hw/intc/arm_gicv3_cpuif.c  |   8 +
 hw/intc/arm_gicv3_kvm.c| 629 -
 hw/intc/armv7m_nvic.c   

Re: [Qemu-devel] [PULL 00/21] target-arm queue

[Peter Maydell]

On 9 January 2017 at 11:53, Peter Maydell  wrote:
> target-arm queue: nothing hugely exciting here, the
> bulk is Andrew's virt-acpi-build refactorings.
>
> thanks
> -- PMM
>
> The following changes since commit ffe22bf51065dd33022cf91f77a821d1f11c250d:
>
>   Merge remote-tracking branch 'remotes/gonglei/tags/cryptodev-next-20161224' 
> into staging (2017-01-06 15:18:09 +)
>
> are available in the git repository at:
>
>   git://git.linaro.org/people/pmaydell/qemu-arm.git 
> tags/pull-target-arm-20170109
>
> for you to fetch changes up to 556899fc1965d82f5c4a3ba6a0be3b1193e2c4b2:
>
>   hw/ssi/imx_spi.c: Remove MSGDATA register support (2017-01-09 11:50:23 
> +)
>
> 
> target-arm queue:
>  * i2c: Allow I2C devices to NAK start events
>  * hw/char: QOM'ify exynos4210_uart.c
>  * clean up and refactor virt-acpi-build.c
>  * virt-acpi-build: Don't incorrectly claim architectural timer
>to be edge-triggered
>  * m25p80: Don't let rogue SPI controllers cause buffer overruns
>  * imx_spi: Remove broken MSGDATA register support
>
> 

Applied, thanks.

-- PMM

[Qemu-devel] [PULL 00/21] target-arm queue

[Peter Maydell]

target-arm queue: nothing hugely exciting here, the
bulk is Andrew's virt-acpi-build refactorings.

thanks
-- PMM

The following changes since commit ffe22bf51065dd33022cf91f77a821d1f11c250d:

  Merge remote-tracking branch 'remotes/gonglei/tags/cryptodev-next-20161224' 
into staging (2017-01-06 15:18:09 +)

are available in the git repository at:

  git://git.linaro.org/people/pmaydell/qemu-arm.git 
tags/pull-target-arm-20170109

for you to fetch changes up to 556899fc1965d82f5c4a3ba6a0be3b1193e2c4b2:

  hw/ssi/imx_spi.c: Remove MSGDATA register support (2017-01-09 11:50:23 +)


target-arm queue:
 * i2c: Allow I2C devices to NAK start events
 * hw/char: QOM'ify exynos4210_uart.c
 * clean up and refactor virt-acpi-build.c
 * virt-acpi-build: Don't incorrectly claim architectural timer
   to be edge-triggered
 * m25p80: Don't let rogue SPI controllers cause buffer overruns
 * imx_spi: Remove broken MSGDATA register support


Andrew Jones (14):
  hw/arm/virt-acpi-build: add all missing cpu_to_le's
  hw/arm/virt-acpi-build: name GIC CPU Interface Structure appropriately
  hw/arm/virt-acpi-build: gtdt: improve flag naming
  hw/arm/virt-acpi-build: fadt: improve flag naming
  hw/arm/virt: parameter passing cleanups
  hw/arm/virt: use VirtMachineState.gic_version
  hw/arm/virt: eliminate struct VirtGuestInfoState
  hw/arm/virt: remove include/hw/arm/virt-acpi-build.h
  hw/arm/virt: move VirtMachineState/Class to virt.h
  hw/arm/virt: pass VirtMachineState instead of VirtGuestInfo
  hw/arm/virt-acpi-build: remove redundant members from VirtGuestInfo
  hw/arm/virt-acpi-build: don't save VirtGuestInfo on AcpiBuildState
  hw/arm/virt: remove VirtGuestInfo
  hw/arm/virt-acpi-build: Don't incorrectly claim architectural timer to be 
edge-triggered

Corey Minyard (1):
  i2c: Allow I2C devices to NAK start events

Jean-Christophe Dubois (2):
  m25p80: don't let rogue SPI controllers cause buffer overruns
  hw/ssi/imx_spi.c: Remove MSGDATA register support

Peter Maydell (3):
  hw/arm/virt: Merge VirtBoardInfo and VirtMachineState
  hw/arm/virt: Rename 'vbi' variables to 'vms'
  hw/arm/virt: Don't incorrectly claim architectural timer to be 
edge-triggered

xiaoqiang zhao (1):
  hw/char: QOM'ify exynos4210_uart.c

 include/hw/acpi/acpi-defs.h  |  33 +-
 include/hw/arm/virt-acpi-build.h |  47 ---
 include/hw/arm/virt.h|  41 ++-
 include/hw/i2c/i2c.h |  16 +-
 hw/arm/pxa2xx.c  |   4 +-
 hw/arm/tosa.c|   4 +-
 hw/arm/virt-acpi-build.c | 134 
 hw/arm/virt.c| 691 ++-
 hw/arm/z2.c  |   4 +-
 hw/audio/wm8750.c|   4 +-
 hw/block/m25p80.c|  29 +-
 hw/char/exynos4210_uart.c|  16 +-
 hw/display/ssd0303.c |   4 +-
 hw/gpio/max7310.c|   4 +-
 hw/i2c/core.c|  31 +-
 hw/i2c/i2c-ddc.c |   4 +-
 hw/i2c/smbus.c   |  13 +-
 hw/input/lm832x.c|   4 +-
 hw/misc/tmp105.c |   3 +-
 hw/ssi/imx_spi.c |  11 +-
 hw/timer/ds1338.c|   4 +-
 hw/timer/twl92230.c  |   4 +-
 MAINTAINERS  |   2 -
 23 files changed, 572 insertions(+), 535 deletions(-)
 delete mode 100644 include/hw/arm/virt-acpi-build.h

[Qemu-devel] [PULL 00/21] target-arm queue

[Peter Maydell]

Here's the target-arm queue; I'm a bit hesitant about the late-landing
various new board/SoC patches, but they won't affect anybody who isn't
trying to use those boards, so I think it's OK.

(There are a few other patches on list which I definitely want to
get in before rc0 but they need a bit more review time I think.)

thanks
-- PMM


The following changes since commit 0ebc03bc065329eaefb6493f5fa7df08df528f2a:

  util/base64.c: Clean includes (2016-03-16 12:48:11 +)

are available in the git repository at:

  git://git.linaro.org/people/pmaydell/qemu-arm.git 
tags/pull-target-arm-20160316

for you to fetch changes up to 10b27d1ab391dbf36f92e1a33179662082401d7a:

  sd: Fix "info qtree" on boards with SD cards (2016-03-16 17:12:46 +)


target-arm queue:
 * loader: Fix incorrect parameter name in load_image_mr()
 * Implement MRS (banked) and MSR (banked) instructions
 * virt: Implement versioning for machine model
 * i.MX: some initial patches preparing for i.MX6 support
 * new ASPEED AST2400 SoC and palmetto-bmc machine
 * bcm2835: add some more raspi2 devices
 * sd: fix segfault running "info qtree"


Andrew Baumann (2):
  bcm2835_peripherals: enable sdhci pending-insert quirk for raspberry pi
  bcm2835_aux: add emulation of BCM2835 AUX (aka UART1) block

Andrew Jeffery (4):
  hw/timer: Add ASPEED timer device model
  hw/intc: Add (new) ASPEED VIC device model
  hw/arm: Add ASPEED AST2400 SoC model
  hw/arm: Add palmetto-bmc machine

Grégory ESTRADE (3):
  bcm2835_fb: add framebuffer device for Raspberry Pi
  bcm2835_property: implement framebuffer control/configuration properties
  bcm2835_dma: add emulation of Raspberry Pi DMA controller

Jean-Christophe Dubois (6):
  i.MX: Allow GPT timer to rollover.
  i.MX: Rename CCM NOCLK to CLK_NONE for naming consistency.
  i.MX: Remove CCM useless clock computation handling.
  i.MX: Add the CLK_IPG_HIGH clock
  i.MX: Add i.MX6 CCM and ANALOG device.
  i.MX: Add missing descriptions in devices.

Jens Wiklander (1):
  loader: Fix incorrect parameter name in load_image_mr() macro

Peter Maydell (2):
  target-arm: Implement MRS (banked) and MSR (banked) instructions
  sd: Fix "info qtree" on boards with SD cards

Sergey Sorokin (1):
  target-arm: Fix translation level on early translation faults

Wei Huang (2):
  arm: virt: Add an abstract ARM virt machine type
  arm: virt: Move machine class init code to the abstract machine type

 default-configs/arm-softmmu.mak  |   1 +
 hw/arm/Makefile.objs |   1 +
 hw/arm/ast2400.c | 137 +++
 hw/arm/bcm2835_peripherals.c | 103 -
 hw/arm/bcm2836.c |   2 +
 hw/arm/fsl-imx25.c   |   1 +
 hw/arm/fsl-imx31.c   |   1 +
 hw/arm/palmetto-bmc.c|  65 +++
 hw/arm/raspi.c   |  12 +-
 hw/arm/virt.c|  57 ++-
 hw/char/Makefile.objs|   1 +
 hw/char/bcm2835_aux.c| 316 ++
 hw/display/Makefile.objs |   1 +
 hw/display/bcm2835_fb.c  | 424 +++
 hw/dma/Makefile.objs |   1 +
 hw/dma/bcm2835_dma.c | 408 ++
 hw/i2c/imx_i2c.c |   1 +
 hw/intc/Makefile.objs|   1 +
 hw/intc/aspeed_vic.c | 339 +++
 hw/misc/Makefile.objs|   1 +
 hw/misc/bcm2835_property.c   | 139 ++-
 hw/misc/imx25_ccm.c  |  29 +-
 hw/misc/imx31_ccm.c  |  35 +-
 hw/misc/imx6_ccm.c   | 774 +++
 hw/net/imx_fec.c |   1 +
 hw/sd/sd.c   |   6 +-
 hw/timer/Makefile.objs   |   1 +
 hw/timer/aspeed_timer.c  | 449 
 hw/timer/imx_epit.c  |   8 +-
 hw/timer/imx_gpt.c   |  43 +-
 include/hw/arm/ast2400.h |  35 ++
 include/hw/arm/bcm2835_peripherals.h |   6 +
 include/hw/char/bcm2835_aux.h|  33 ++
 include/hw/display/bcm2835_fb.h  |  47 +++
 include/hw/dma/bcm2835_dma.h |  47 +++
 include/hw/intc/aspeed_vic.h |  48 +++
 include/hw/loader.h  |   2 +-
 include/hw/misc/bcm2835_property.h   |   5 +-
 include/hw/misc/imx6_ccm.h   | 197 +
 include/hw/misc/imx_ccm.h|  10 +-
 include/hw/timer/aspeed_timer.h  |  59 +++
 target-arm/helper.c  |  22 +-
 target-arm/helper.h  |   3 +
 target-arm/op_helper.c   | 120 ++
 target-arm/translate.c   | 246 ++-
 trace-events |  16 +
 46 files changed, 4114 insertions(+), 140 deletions(-)
 create mode 

Re: [Qemu-devel] [PULL 00/21] target-arm queue

[Peter Maydell]

On 16 March 2016 at 17:18, Peter Maydell  wrote:
> Here's the target-arm queue; I'm a bit hesitant about the late-landing
> various new board/SoC patches, but they won't affect anybody who isn't
> trying to use those boards, so I think it's OK.
>
> (There are a few other patches on list which I definitely want to
> get in before rc0 but they need a bit more review time I think.)
>
> thanks
> -- PMM
>
>
> The following changes since commit 0ebc03bc065329eaefb6493f5fa7df08df528f2a:
>
>   util/base64.c: Clean includes (2016-03-16 12:48:11 +)
>
> are available in the git repository at:
>
>   git://git.linaro.org/people/pmaydell/qemu-arm.git 
> tags/pull-target-arm-20160316
>
> for you to fetch changes up to 10b27d1ab391dbf36f92e1a33179662082401d7a:
>
>   sd: Fix "info qtree" on boards with SD cards (2016-03-16 17:12:46 +)
>
> 
> target-arm queue:
>  * loader: Fix incorrect parameter name in load_image_mr()
>  * Implement MRS (banked) and MSR (banked) instructions
>  * virt: Implement versioning for machine model
>  * i.MX: some initial patches preparing for i.MX6 support
>  * new ASPEED AST2400 SoC and palmetto-bmc machine
>  * bcm2835: add some more raspi2 devices
>  * sd: fix segfault running "info qtree"

Some versions of gcc appear to give false positive 'may be used
uninitialized' warnings about the msr/mrs code:

/home/petmay01/linaro/qemu-for-merges/target-arm/translate.c: In
function ‘gen_msr_banked
.isra.45’:
/home/petmay01/linaro/qemu-for-merges/target-arm/translate.c:4321:17:
error: ‘tgtmode’ ma
y be used uninitialized in this function [-Werror=maybe-uninitialized]
 tcg_tgtmode = tcg_const_i32(tgtmode);
 ^
/home/petmay01/linaro/qemu-for-merges/target-arm/translate.c:4322:15:
error: ‘regno’ may be used uninitialized in this function
[-Werror=maybe-uninitialized]
 tcg_regno = tcg_const_i32(regno);
   ^
/home/petmay01/linaro/qemu-for-merges/target-arm/translate.c: In
function ‘gen_mrs_banked.isra.48’:
/home/petmay01/linaro/qemu-for-merges/target-arm/translate.c:4343:17:
error: ‘tgtmode’ may be used uninitialized in this function
[-Werror=maybe-uninitialized]
 tcg_tgtmode = tcg_const_i32(tgtmode);
 ^
/home/petmay01/linaro/qemu-for-merges/target-arm/translate.c:4344:15:
error: ‘regno’ may be used uninitialized in this function
[-Werror=maybe-uninitialized]
 tcg_regno = tcg_const_i32(regno);
   ^

Fixup:
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -4308,7 +4308,7 @@ undef:
 static void gen_msr_banked(DisasContext *s, int r, int sysm, int rn)
 {
 TCGv_i32 tcg_reg, tcg_tgtmode, tcg_regno;
-int tgtmode, regno;
+int tgtmode = 0, regno = 0;

 if (!msr_banked_access_decode(s, r, sysm, rn, , )) {
 return;
@@ -4330,7 +4330,7 @@ static void gen_msr_banked(DisasContext *s, int
r, int sysm, int rn)
 static void gen_mrs_banked(DisasContext *s, int r, int sysm, int rn)
 {
 TCGv_i32 tcg_reg, tcg_tgtmode, tcg_regno;
-int tgtmode, regno;
+int tgtmode = 0, regno = 0;

 if (!msr_banked_access_decode(s, r, sysm, rn, , )) {
 return;

which I'll squash into the appropriate patch and respin.

thanks
-- PMM

Re: [Qemu-devel] [PULL 00/21] target-arm queue

[Peter Maydell]

On 16 March 2016 at 17:18, Peter Maydell  wrote:
> Here's the target-arm queue; I'm a bit hesitant about the late-landing
> various new board/SoC patches, but they won't affect anybody who isn't
> trying to use those boards, so I think it's OK.
>
> (There are a few other patches on list which I definitely want to
> get in before rc0 but they need a bit more review time I think.)
>
> thanks
> -- PMM
>
>
> The following changes since commit 0ebc03bc065329eaefb6493f5fa7df08df528f2a:
>
>   util/base64.c: Clean includes (2016-03-16 12:48:11 +)
>
> are available in the git repository at:
>
>   git://git.linaro.org/people/pmaydell/qemu-arm.git 
> tags/pull-target-arm-20160316
>
> for you to fetch changes up to 10b27d1ab391dbf36f92e1a33179662082401d7a:
>
>   sd: Fix "info qtree" on boards with SD cards (2016-03-16 17:12:46 +)

Respin with fix now applied to master.

-- PMM

Re: [Qemu-devel] [PULL 00/21] target-arm queue

[Peter Maydell]

On 18 May 2015 at 20:15, Peter Maydell peter.mayd...@linaro.org wrote:
 target-arm queue: mostly the new Xilinx board, plus a handful
 of other minor things.

 -- PMM


 The following changes since commit 385057cbec9b4a0eb6150330c572e875ed714965:

   Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2015-05-15' 
 into staging (2015-05-15 17:51:20 +0100)

 are available in the git repository at:


   git://git.linaro.org/people/pmaydell/qemu-arm.git 
 tags/pull-target-arm-20150518-3

 for you to fetch changes up to 18084b2f71b22b3ec3bf4828b8cb83d1d39e8502:

   target-arm: Remove unneeded '+' (2015-05-18 20:04:19 +0100)

 
 target-arm:
  * New board model: xlnx-ep108
  * Some more preparation for AArch64 EL2/EL3
  * Fix bugs in access checking for generic counter registers
  * Remove a stray '+' sign

 

Applied, thanks.

-- PMM

[Qemu-devel] [PULL 00/21] target-arm queue

[Peter Maydell]

target-arm queue: mostly the new Xilinx board, plus a handful
of other minor things.

-- PMM


The following changes since commit 385057cbec9b4a0eb6150330c572e875ed714965:

  Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2015-05-15' into 
staging (2015-05-15 17:51:20 +0100)

are available in the git repository at:


  git://git.linaro.org/people/pmaydell/qemu-arm.git 
tags/pull-target-arm-20150518-3

for you to fetch changes up to 18084b2f71b22b3ec3bf4828b8cb83d1d39e8502:

  target-arm: Remove unneeded '+' (2015-05-18 20:04:19 +0100)


target-arm:
 * New board model: xlnx-ep108
 * Some more preparation for AArch64 EL2/EL3
 * Fix bugs in access checking for generic counter registers
 * Remove a stray '+' sign


Edgar E. Iglesias (3):
  target-arm: Correct accessfn for CNTP_{CT}VAL_EL0
  target-arm: Correct accessfn for CNTV_TVAL_EL0
  target-arm: Remove unneeded '+'

Greg Bellows (3):
  target-arm: Add TTBR regime function and use
  target-arm: Add EL3 and EL2 TCR checking
  target-arm: Add WFx syndrome function

Peter Crosthwaite (14):
  target-arm: cpu64: generalise name of A57 regs
  target-arm: cpu64: Add support for Cortex-A53
  arm: Introduce Xilinx ZynqMP SoC
  arm: xlnx-zynqmp: Add GIC
  arm: xlnx-zynqmp: Connect CPU Timers to GIC
  net: cadence_gem: Clean up variable names
  net: cadence_gem: Split state struct and type into header
  arm: xlnx-zynqmp: Add GEM support
  char: cadence_uart: Clean up variable names
  char: cadence_uart: Split state struct and type into header
  arm: xlnx-zynqmp: Add UART support
  arm: Add xlnx-ep108 machine
  arm: xlnx-ep108: Add external RAM
  arm: xlnx-ep108: Add bootloading

Timothy Baldwin (1):
  linux-user/arm: Correct TARGET_NR_timerfd to TARGET_NR_timerfd_create

 default-configs/aarch64-softmmu.mak |   2 +-
 hw/arm/Makefile.objs|   1 +
 hw/arm/xlnx-ep108.c |  82 ++
 hw/arm/xlnx-zynqmp.c| 211 
 hw/char/cadence_uart.c  | 115 
 hw/net/cadence_gem.c|  95 +---
 include/hw/arm/xlnx-zynqmp.h|  58 ++
 include/hw/char/cadence_uart.h  |  53 +
 include/hw/net/cadence_gem.h|  73 +
 linux-user/arm/syscall_nr.h |   2 +-
 target-arm/cpu64.c  |  61 ++-
 target-arm/helper.c |  75 +
 target-arm/internals.h  |   6 +
 13 files changed, 671 insertions(+), 163 deletions(-)
 create mode 100644 hw/arm/xlnx-ep108.c
 create mode 100644 hw/arm/xlnx-zynqmp.c
 create mode 100644 include/hw/arm/xlnx-zynqmp.h
 create mode 100644 include/hw/char/cadence_uart.h
 create mode 100644 include/hw/net/cadence_gem.h

[Qemu-devel] [PULL 00/21] target-arm queue

[Peter Maydell]

Hi; this is my target-arm queue. Contents:
 * my 'get rid of arm_pic' series
 * generic timer support for A15
 * a few other minor fixes

To avoid potential conflicts between a target-arm pullreq
and an arm-devs pullreq, I've just put all these ARM related
patches in the same tree even though a few of them could
strictly speaking have gone into an arm-devs tree. (I'd
actually prefer to combine target-arm.next and arm-devs.next
into a single tree in future, since I think some of the admin
reasons for the original split have now gone away. Let me know
if this is going to be a problem and I'll maintain the split.)

Please pull.

thanks
--PMM


The following changes since commit f202039811d8746b0586d2fd5f61de6c8cf68056:

  Open up 1.7 development branch (2013-08-15 15:41:13 -0500)

are available in the git repository at:

  git://git.linaro.org/people/pmaydell/qemu-arm.git 
tags/pull-target-arm-20130820

for you to fetch changes up to 230058106ab26de9b876158dbe27d60719f01f51:

  hw/timer/imx_epit: Simplify and fix imx_epit implementation (2013-08-20 
14:54:32 +0100)


target-arm queue


Peter Chubb (1):
  hw/timer/imx_epit: Simplify and fix imx_epit implementation

Peter Maydell (20):
  target-arm: Implement 'int' loglevel
  target-arm: Make IRQ and FIQ gpio lines on the CPU object
  hw/arm/armv7m: Don't use arm_pic_init_cpu()
  hw/arm/exynos4210: Don't use arm_pic_init_cpu()
  hw/arm/highbank: Don't use arm_pic_init_cpu()
  hw/arm/integratorcp: Don't use arm_pic_init_cpu()
  hw/arm/kzm: Don't use arm_pic_init_cpu()
  hw/arm/musicpal: Don't use arm_pic_init_cpu()
  hw/arm/omap*: Don't use arm_pic_init_cpu()
  hw/arm/realview: Don't use arm_pic_init_cpu()
  hw/arm/strongarm: Don't use arm_pic_init_cpu()
  hw/arm/versatilepb: Don't use arm_pic_init_cpu()
  hw/arm/vexpress: Don't use arm_pic_init_cpu()
  hw/arm/xilinx_zynq: Don't use arm_pic_init_cpu()
  hw/arm/pic_cpu: Remove the now-unneeded arm_pic_init_cpu()
  target-arm: Allow raw_read() and raw_write() to handle 64 bit regs
  target-arm: Support coprocessor registers which do I/O
  target-arm: Implement the generic timer
  hw/cpu/a15mpcore: Wire generic timer outputs to GIC inputs
  default-configs: Fix A9MP and A15MP config names

 default-configs/arm-softmmu.mak |4 +-
 hw/arm/Makefile.objs|2 +-
 hw/arm/armv7m.c |5 +-
 hw/arm/exynos4210.c |   16 +-
 hw/arm/highbank.c   |4 +-
 hw/arm/integratorcp.c   |7 +-
 hw/arm/kzm.c|8 +-
 hw/arm/musicpal.c   |4 +-
 hw/arm/omap1.c  |8 +-
 hw/arm/omap2.c  |8 +-
 hw/arm/pic_cpu.c|   68 -
 hw/arm/realview.c   |4 +-
 hw/arm/strongarm.c  |6 +-
 hw/arm/versatilepb.c|7 +-
 hw/arm/vexpress.c   |8 +-
 hw/arm/xilinx_zynq.c|7 +-
 hw/cpu/Makefile.objs|4 +-
 hw/cpu/a15mpcore.c  |   18 +++
 hw/timer/imx_epit.c |   94 +---
 include/hw/arm/arm.h|5 -
 target-arm/cpu-qom.h|9 ++
 target-arm/cpu.c|   67 +
 target-arm/cpu.h|   27 +++-
 target-arm/helper.c |  310 ++-
 target-arm/machine.c|8 +-
 target-arm/translate.c  |   16 +-
 26 files changed, 514 insertions(+), 210 deletions(-)
 delete mode 100644 hw/arm/pic_cpu.c