Re: [PULL 00/25] riscv-to-apply queue
On 6/9/22 21:26, Alistair Francis wrote: From: Alistair Francis The following changes since commit 9cc1bf1ebca550f8d90f967ccd2b6d2e00e81387: Merge tag 'pull-xen-20220609' of https://xenbits.xen.org/git-http/people/aperard/qemu-dm into staging (2022-06-09 08:25:17 -0700) are available in the Git repository at: g...@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20220610 for you to fetch changes up to 07314158f6aa4d2589520c194a7531b9364a8d54: target/riscv: trans_rvv: Avoid assert for RV32 and e64 (2022-06-10 09:42:12 +1000) Fourth RISC-V PR for QEMU 7.1 * Update MAINTAINERS * Add support for Zmmul extension * Fixup FDT errors when supplying device tree from the command line for virt machine * Avoid overflowing the addr_config buffer in the SiFive PLIC * Support -device loader addresses above 2GB * Correctly wake from WFI on VS-level external interrupts * Fixes for RV128 support * Support Vector extension tail agnostic setting elements' bits to all 1s * Don't expose the CPU properties on named CPUs * Fix vector extension assert for RV32 Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/7.1 as appropriate. r~ Alistair Francis (4): MAINTAINERS: Cover hw/core/uboot_image.h within Generic Loader section hw/intc: sifive_plic: Avoid overflowing the addr_config buffer target/riscv: Don't expose the CPU properties on names CPUs target/riscv: trans_rvv: Avoid assert for RV32 and e64 Andrew Bresticker (1): target/riscv: Wake on VS-level external interrupts Atish Patra (1): hw/riscv: virt: Generate fw_cfg DT node correctly Frédéric Pétrot (1): target/riscv/debug.c: keep experimental rv128 support working Jamie Iles (1): hw/core/loader: return image sizes as ssize_t Weiwei Li (1): target/riscv: add support for zmmul extension v0.1 eopXD (16): target/riscv: rvv: Prune redundant ESZ, DSZ parameter passed target/riscv: rvv: Prune redundant access_type parameter passed target/riscv: rvv: Rename ambiguous esz target/riscv: rvv: Early exit when vstart >= vl target/riscv: rvv: Add tail agnostic for vv instructions target/riscv: rvv: Add tail agnostic for vector load / store instructions target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions target/riscv: rvv: Add tail agnostic for vector integer shift instructions target/riscv: rvv: Add tail agnostic for vector integer comparison instructions target/riscv: rvv: Add tail agnostic for vector integer merge and move instructions target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic instructions target/riscv: rvv: Add tail agnostic for vector floating-point instructions target/riscv: rvv: Add tail agnostic for vector reduction instructions target/riscv: rvv: Add tail agnostic for vector mask instructions target/riscv: rvv: Add tail agnostic for vector permutation instructions target/riscv: rvv: Add option 'rvv_ta_all_1s' to enable optional tail agnostic behavior include/hw/loader.h | 55 +- target/riscv/cpu.h |4 + target/riscv/internals.h|6 +- hw/arm/armv7m.c |2 +- hw/arm/boot.c |8 +- hw/core/generic-loader.c|2 +- hw/core/loader.c| 81 +- hw/i386/x86.c |2 +- hw/intc/sifive_plic.c | 19 +- hw/riscv/boot.c |5 +- hw/riscv/virt.c | 28 +- target/riscv/cpu.c | 68 +- target/riscv/cpu_helper.c |4 +- target/riscv/debug.c|2 + target/riscv/translate.c|4 + target/riscv/vector_helper.c| 1588 +++ target/riscv/insn_trans/trans_rvm.c.inc | 18 +- target/riscv/insn_trans/trans_rvv.c.inc | 106 ++- MAINTAINERS |1 + 19 files changed, 1244 insertions(+), 759 deletions(-)
[PULL 00/25] riscv-to-apply queue
From: Alistair Francis The following changes since commit 9cc1bf1ebca550f8d90f967ccd2b6d2e00e81387: Merge tag 'pull-xen-20220609' of https://xenbits.xen.org/git-http/people/aperard/qemu-dm into staging (2022-06-09 08:25:17 -0700) are available in the Git repository at: g...@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20220610 for you to fetch changes up to 07314158f6aa4d2589520c194a7531b9364a8d54: target/riscv: trans_rvv: Avoid assert for RV32 and e64 (2022-06-10 09:42:12 +1000) Fourth RISC-V PR for QEMU 7.1 * Update MAINTAINERS * Add support for Zmmul extension * Fixup FDT errors when supplying device tree from the command line for virt machine * Avoid overflowing the addr_config buffer in the SiFive PLIC * Support -device loader addresses above 2GB * Correctly wake from WFI on VS-level external interrupts * Fixes for RV128 support * Support Vector extension tail agnostic setting elements' bits to all 1s * Don't expose the CPU properties on named CPUs * Fix vector extension assert for RV32 Alistair Francis (4): MAINTAINERS: Cover hw/core/uboot_image.h within Generic Loader section hw/intc: sifive_plic: Avoid overflowing the addr_config buffer target/riscv: Don't expose the CPU properties on names CPUs target/riscv: trans_rvv: Avoid assert for RV32 and e64 Andrew Bresticker (1): target/riscv: Wake on VS-level external interrupts Atish Patra (1): hw/riscv: virt: Generate fw_cfg DT node correctly Frédéric Pétrot (1): target/riscv/debug.c: keep experimental rv128 support working Jamie Iles (1): hw/core/loader: return image sizes as ssize_t Weiwei Li (1): target/riscv: add support for zmmul extension v0.1 eopXD (16): target/riscv: rvv: Prune redundant ESZ, DSZ parameter passed target/riscv: rvv: Prune redundant access_type parameter passed target/riscv: rvv: Rename ambiguous esz target/riscv: rvv: Early exit when vstart >= vl target/riscv: rvv: Add tail agnostic for vv instructions target/riscv: rvv: Add tail agnostic for vector load / store instructions target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions target/riscv: rvv: Add tail agnostic for vector integer shift instructions target/riscv: rvv: Add tail agnostic for vector integer comparison instructions target/riscv: rvv: Add tail agnostic for vector integer merge and move instructions target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic instructions target/riscv: rvv: Add tail agnostic for vector floating-point instructions target/riscv: rvv: Add tail agnostic for vector reduction instructions target/riscv: rvv: Add tail agnostic for vector mask instructions target/riscv: rvv: Add tail agnostic for vector permutation instructions target/riscv: rvv: Add option 'rvv_ta_all_1s' to enable optional tail agnostic behavior include/hw/loader.h | 55 +- target/riscv/cpu.h |4 + target/riscv/internals.h|6 +- hw/arm/armv7m.c |2 +- hw/arm/boot.c |8 +- hw/core/generic-loader.c|2 +- hw/core/loader.c| 81 +- hw/i386/x86.c |2 +- hw/intc/sifive_plic.c | 19 +- hw/riscv/boot.c |5 +- hw/riscv/virt.c | 28 +- target/riscv/cpu.c | 68 +- target/riscv/cpu_helper.c |4 +- target/riscv/debug.c|2 + target/riscv/translate.c|4 + target/riscv/vector_helper.c| 1588 +++ target/riscv/insn_trans/trans_rvm.c.inc | 18 +- target/riscv/insn_trans/trans_rvv.c.inc | 106 ++- MAINTAINERS |1 + 19 files changed, 1244 insertions(+), 759 deletions(-)
Re: [PULL 00/25] riscv-to-apply queue
On 4/28/22 21:30, Alistair Francis wrote:
From: Alistair Francis
The following changes since commit f22833602095b05733bceaddeb20f3edfced3c07:
Merge tag 'pull-target-arm-20220428' of
https://git.linaro.org/people/pmaydell/qemu-arm into staging (2022-04-28
08:34:17 -0700)
are available in the Git repository at:
g...@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20220429
for you to fetch changes up to 325b7c4e7582c229d28c47123c3b986ed948eb84:
hw/riscv: Enable TPM backends (2022-04-29 10:48:48 +1000)
Second RISC-V PR for QEMU 7.1
* Improve device tree generation
* Support configuarable marchid, mvendorid, mipid CSR values
* Add support for the Zbkb, Zbkc, Zbkx, Zknd/Zkne, Zknh, Zksed/Zksh and Zkr
extensions
* Fix incorrect PTE merge in walk_pte
* Add TPM support to the virt board
Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/7.1 as
appropriate.
r~
Alistair Francis (6):
hw/riscv: virt: Add a machine done notifier
hw/core: Move the ARM sysbus-fdt to core
hw/riscv: virt: Create a platform bus
hw/riscv: virt: Add support for generating platform FDT entries
hw/riscv: virt: Add device plug support
hw/riscv: Enable TPM backends
Bin Meng (2):
hw/riscv: spike: Add '/chosen/stdout-path' in device tree unconditionally
hw/riscv: Don't add empty bootargs to device tree
Frank Chang (1):
target/riscv: Support configuarable marchid, mvendorid, mipid CSR values
Ralf Ramsauer (1):
target/riscv: Fix incorrect PTE merge in walk_pte
Weiwei Li (15):
target/riscv: rvk: add cfg properties for zbk* and zk*
target/riscv: rvk: add support for zbkb extension
target/riscv: rvk: add support for zbkc extension
target/riscv: rvk: add support for zbkx extension
crypto: move sm4_sbox from target/arm
target/riscv: rvk: add support for zknd/zkne extension in RV32
target/riscv: rvk: add support for zkne/zknd extension in RV64
target/riscv: rvk: add support for sha256 related instructions in zknh
extension
target/riscv: rvk: add support for sha512 related instructions for RV32
in zknh extension
target/riscv: rvk: add support for sha512 related instructions for RV64
in zknh extension
target/riscv: rvk: add support for zksed/zksh extension
target/riscv: rvk: add CSR support for Zkr
disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructions
target/riscv: rvk: expose zbk* and zk* properties
target/riscv: add scalar crypto related extenstion strings to isa_string
docs/system/riscv/virt.rst | 20 ++
include/crypto/sm4.h| 6 +
include/hw/{arm => core}/sysbus-fdt.h | 0
include/hw/riscv/virt.h | 8 +-
target/riscv/cpu.h | 17 ++
target/riscv/cpu_bits.h | 9 +
target/riscv/helper.h | 22 ++
target/riscv/pmp.h | 8 +-
target/riscv/insn32.decode | 97 ++--
crypto/sm4.c| 49
disas/riscv.c | 173 +-
hw/arm/virt.c | 2 +-
hw/arm/xlnx-versal-virt.c | 1 -
hw/{arm => core}/sysbus-fdt.c | 2 +-
hw/riscv/microchip_pfsoc.c | 2 +-
hw/riscv/sifive_u.c | 2 +-
hw/riscv/spike.c| 7 +-
hw/riscv/virt.c | 319 +-
target/arm/crypto_helper.c | 36 +--
target/riscv/bitmanip_helper.c | 80 +++
target/riscv/cpu.c | 58 +
target/riscv/crypto_helper.c| 302
target/riscv/csr.c | 118 +-
target/riscv/monitor.c | 11 +-
target/riscv/op_helper.c| 9 +
target/riscv/translate.c| 8 +
target/riscv/insn_trans/trans_rvb.c.inc | 116 --
target/riscv/insn_trans/trans_rvk.c.inc | 391
crypto/meson.build | 1 +
hw/arm/meson.build | 1 -
hw/core/meson.build | 1 +
hw/riscv/Kconfig| 2 +
target/riscv/meson.build| 3 +-
33 files changed, 1682 insertions(+), 199 deletions(-)
create mode 100644 include/crypto/sm4.h
rename include/hw/{arm => core}/sysbus-fdt.h (100%)
create mode 100644 crypto/sm4.c
rename hw/{arm => core}/sysbus-fdt.c (99%)
create mode 100644 target/riscv/crypto_helper.c
create mode 100644 target/riscv/insn_trans/trans_rvk.c.inc
[PULL 00/25] riscv-to-apply queue
From: Alistair Francis
The following changes since commit f22833602095b05733bceaddeb20f3edfced3c07:
Merge tag 'pull-target-arm-20220428' of
https://git.linaro.org/people/pmaydell/qemu-arm into staging (2022-04-28
08:34:17 -0700)
are available in the Git repository at:
g...@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20220429
for you to fetch changes up to 325b7c4e7582c229d28c47123c3b986ed948eb84:
hw/riscv: Enable TPM backends (2022-04-29 10:48:48 +1000)
Second RISC-V PR for QEMU 7.1
* Improve device tree generation
* Support configuarable marchid, mvendorid, mipid CSR values
* Add support for the Zbkb, Zbkc, Zbkx, Zknd/Zkne, Zknh, Zksed/Zksh and Zkr
extensions
* Fix incorrect PTE merge in walk_pte
* Add TPM support to the virt board
Alistair Francis (6):
hw/riscv: virt: Add a machine done notifier
hw/core: Move the ARM sysbus-fdt to core
hw/riscv: virt: Create a platform bus
hw/riscv: virt: Add support for generating platform FDT entries
hw/riscv: virt: Add device plug support
hw/riscv: Enable TPM backends
Bin Meng (2):
hw/riscv: spike: Add '/chosen/stdout-path' in device tree unconditionally
hw/riscv: Don't add empty bootargs to device tree
Frank Chang (1):
target/riscv: Support configuarable marchid, mvendorid, mipid CSR values
Ralf Ramsauer (1):
target/riscv: Fix incorrect PTE merge in walk_pte
Weiwei Li (15):
target/riscv: rvk: add cfg properties for zbk* and zk*
target/riscv: rvk: add support for zbkb extension
target/riscv: rvk: add support for zbkc extension
target/riscv: rvk: add support for zbkx extension
crypto: move sm4_sbox from target/arm
target/riscv: rvk: add support for zknd/zkne extension in RV32
target/riscv: rvk: add support for zkne/zknd extension in RV64
target/riscv: rvk: add support for sha256 related instructions in zknh
extension
target/riscv: rvk: add support for sha512 related instructions for RV32
in zknh extension
target/riscv: rvk: add support for sha512 related instructions for RV64
in zknh extension
target/riscv: rvk: add support for zksed/zksh extension
target/riscv: rvk: add CSR support for Zkr
disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructions
target/riscv: rvk: expose zbk* and zk* properties
target/riscv: add scalar crypto related extenstion strings to isa_string
docs/system/riscv/virt.rst | 20 ++
include/crypto/sm4.h| 6 +
include/hw/{arm => core}/sysbus-fdt.h | 0
include/hw/riscv/virt.h | 8 +-
target/riscv/cpu.h | 17 ++
target/riscv/cpu_bits.h | 9 +
target/riscv/helper.h | 22 ++
target/riscv/pmp.h | 8 +-
target/riscv/insn32.decode | 97 ++--
crypto/sm4.c| 49
disas/riscv.c | 173 +-
hw/arm/virt.c | 2 +-
hw/arm/xlnx-versal-virt.c | 1 -
hw/{arm => core}/sysbus-fdt.c | 2 +-
hw/riscv/microchip_pfsoc.c | 2 +-
hw/riscv/sifive_u.c | 2 +-
hw/riscv/spike.c| 7 +-
hw/riscv/virt.c | 319 +-
target/arm/crypto_helper.c | 36 +--
target/riscv/bitmanip_helper.c | 80 +++
target/riscv/cpu.c | 58 +
target/riscv/crypto_helper.c| 302
target/riscv/csr.c | 118 +-
target/riscv/monitor.c | 11 +-
target/riscv/op_helper.c| 9 +
target/riscv/translate.c| 8 +
target/riscv/insn_trans/trans_rvb.c.inc | 116 --
target/riscv/insn_trans/trans_rvk.c.inc | 391
crypto/meson.build | 1 +
hw/arm/meson.build | 1 -
hw/core/meson.build | 1 +
hw/riscv/Kconfig| 2 +
target/riscv/meson.build| 3 +-
33 files changed, 1682 insertions(+), 199 deletions(-)
create mode 100644 include/crypto/sm4.h
rename include/hw/{arm => core}/sysbus-fdt.h (100%)
create mode 100644 crypto/sm4.c
rename hw/{arm => core}/sysbus-fdt.c (99%)
create mode 100644 target/riscv/crypto_helper.c
create mode 100644 target/riscv/insn_trans/trans_rvk.c.inc
