[PULL 002/113] target/i386: Support up to 32768 CPUs without IRQ remapping

2020-12-10 Thread Paolo Bonzini
From: David Woodhouse The IOAPIC has an 'Extended Destination ID' field in its RTE, which maps to bits 11-4 of the MSI address. Since those address bits fall within a given 4KiB page they were historically non-trivial to use on real hardware. The Intel IOMMU uses the lowest bit to indicate a

[PULL 002/113] target/i386: Support up to 32768 CPUs without IRQ remapping

2020-12-02 Thread Paolo Bonzini
From: David Woodhouse The IOAPIC has an 'Extended Destination ID' field in its RTE, which maps to bits 11-4 of the MSI address. Since those address bits fall within a given 4KiB page they were historically non-trivial to use on real hardware. The Intel IOMMU uses the lowest bit to indicate a