Re: [Qemu-devel] Re: [PATCH 2/2] tcg-sparc: Implement setcond, setcond2.
Thanks, applied. Please remember the Signed-off-by: line.
On Mon, Feb 15, 2010 at 11:22 PM, Richard Henderson r...@twiddle.net wrote:
On 02/13/2010 02:01 PM, Blue Swirl wrote:
On Tue, Feb 9, 2010 at 11:37 PM, Richard Henderson r...@twiddle.net wrote:
---
tcg/sparc/tcg-target.c | 126
1 files changed, 126 insertions(+), 0 deletions(-)
Something's wrong with the patch...
Oops. The tree wasn't properly committed when I
extracted the patch. Here's that last again.
r~
---
commit 8f76ac8882ff2b0d9db402352b9cf632cc92f84f
Author: Richard Henderson r...@twiddle.net
Date: Mon Feb 15 13:19:49 2010 -0800
tcg-sparc: Implement setcond, setcond2.
diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c
index dd7a598..5b4347a 100644
--- a/tcg/sparc/tcg-target.c
+++ b/tcg/sparc/tcg-target.c
@@ -194,6 +194,7 @@ static inline int tcg_target_const_match(tcg_target_long
val,
#define INSN_RS2(x) (x)
#define INSN_ASI(x) ((x) 5)
+#define INSN_IMM11(x) ((1 13) | ((x) 0x7ff))
#define INSN_IMM13(x) ((1 13) | ((x) 0x1fff))
#define INSN_OFF19(x) (((x) 2) 0x07)
#define INSN_OFF22(x) (((x) 2) 0x3f)
@@ -217,6 +218,9 @@ static inline int tcg_target_const_match(tcg_target_long
val,
#define COND_VC 0xf
#define BA (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2))
+#define MOVCC_ICC (1 18)
+#define MOVCC_XCC (1 18 | 1 12)
+
#define ARITH_ADD (INSN_OP(2) | INSN_OP3(0x00))
#define ARITH_ADDCC (INSN_OP(2) | INSN_OP3(0x10))
#define ARITH_AND (INSN_OP(2) | INSN_OP3(0x01))
@@ -233,6 +237,7 @@ static inline int tcg_target_const_match(tcg_target_long
val,
#define ARITH_MULX (INSN_OP(2) | INSN_OP3(0x09))
#define ARITH_UDIVX (INSN_OP(2) | INSN_OP3(0x0d))
#define ARITH_SDIVX (INSN_OP(2) | INSN_OP3(0x2d))
+#define ARITH_MOVCC (INSN_OP(2) | INSN_OP3(0x2c))
#define SHIFT_SLL (INSN_OP(2) | INSN_OP3(0x25))
#define SHIFT_SRL (INSN_OP(2) | INSN_OP3(0x26))
@@ -580,6 +585,109 @@ static void tcg_out_brcond2_i32(TCGContext *s, int cond,
}
#endif
+static void tcg_out_setcond_i32(TCGContext *s, int cond, TCGArg ret,
+ TCGArg c1, TCGArg c2, int c2const)
+{
+ TCGArg t;
+
+ /* For 32-bit comparisons, we can play games with ADDX/SUBX. */
+ switch (cond) {
+ case TCG_COND_EQ:
+ case TCG_COND_NE:
+ if (c2 != 0) {
+ tcg_out_arithc(s, ret, c1, c2, c2const, ARITH_XOR);
+ }
+ c1 = TCG_REG_G0, c2 = ret, c2const = 0;
+ cond = (cond == TCG_COND_EQ ? TCG_COND_LEU : TCG_COND_LTU);
+ break;
+
+ case TCG_COND_GTU:
+ case TCG_COND_GEU:
+ if (c2const c2 != 0) {
+ tcg_out_movi_imm13(s, TCG_REG_I5, c2);
+ c2 = TCG_REG_I5;
+ }
+ t = c1, c1 = c2, c2 = t, c2const = 0;
+ cond = tcg_swap_cond(cond);
+ break;
+
+ case TCG_COND_LTU:
+ case TCG_COND_LEU:
+ break;
+
+ default:
+ tcg_out_cmp(s, c1, c2, c2const);
+#if defined(__sparc_v9__) || defined(__sparc_v8plus__)
+ tcg_out_movi_imm13(s, ret, 0);
+ tcg_out32 (s, ARITH_MOVCC | INSN_RD(ret)
+ | INSN_RS1(tcg_cond_to_bcond[cond])
+ | MOVCC_ICC | INSN_IMM11(1));
+#else
+ t = gen_new_label();
+ tcg_out_branch_i32(s, INSN_COND(tcg_cond_to_bcond[cond], 1), t);
+ tcg_out_movi_imm13(s, ret, 1);
+ tcg_out_movi_imm13(s, ret, 0);
+ tcg_out_label(s, t, (tcg_target_long)s-code_ptr);
+#endif
+ return;
+ }
+
+ tcg_out_cmp(s, c1, c2, c2const);
+ if (cond == TCG_COND_LTU) {
+ tcg_out_arithi(s, ret, TCG_REG_G0, 0, ARITH_ADDX);
+ } else {
+ tcg_out_arithi(s, ret, TCG_REG_G0, -1, ARITH_SUBX);
+ }
+}
+
+#if TCG_TARGET_REG_BITS == 64
+static void tcg_out_setcond_i64(TCGContext *s, int cond, TCGArg ret,
+ TCGArg c1, TCGArg c2, int c2const)
+{
+ tcg_out_cmp(s, c1, c2, c2const);
+ tcg_out_movi_imm13(s, ret, 0);
+ tcg_out32 (s, ARITH_MOVCC | INSN_RD(ret)
+ | INSN_RS1(tcg_cond_to_bcond[cond])
+ | MOVCC_XCC | INSN_IMM11(1));
+}
+#else
+static void tcg_out_setcond2_i32(TCGContext *s, int cond, TCGArg ret,
+ TCGArg al, TCGArg ah,
+ TCGArg bl, int blconst,
+ TCGArg bh, int bhconst)
+{
+ int lab;
+
+ switch (cond) {
+ case TCG_COND_EQ:
+ tcg_out_setcond_i32(s, TCG_COND_EQ, TCG_REG_I5, al, bl, blconst);
+ tcg_out_setcond_i32(s, TCG_COND_EQ, ret, ah, bh, bhconst);
+ tcg_out_arith(s, ret, ret, TCG_REG_I5, ARITH_AND);
+ break;
+
+ case TCG_COND_NE:
+ tcg_out_setcond_i32(s, TCG_COND_NE, TCG_REG_I5, al, al, blconst);
+ tcg_out_setcond_i32(s, TCG_COND_NE, ret, ah, bh, bhconst);
+ tcg_out_arith(s, ret, ret,
Re: [Qemu-devel] Re: [PATCH 2/2] tcg-sparc: Implement setcond, setcond2.
On 02/13/2010 02:01 PM, Blue Swirl wrote:
On Tue, Feb 9, 2010 at 11:37 PM, Richard Henderson r...@twiddle.net wrote:
---
tcg/sparc/tcg-target.c | 126
1 files changed, 126 insertions(+), 0 deletions(-)
Something's wrong with the patch...
Oops. The tree wasn't properly committed when I
extracted the patch. Here's that last again.
r~
---
commit 8f76ac8882ff2b0d9db402352b9cf632cc92f84f
Author: Richard Henderson r...@twiddle.net
Date: Mon Feb 15 13:19:49 2010 -0800
tcg-sparc: Implement setcond, setcond2.
diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c
index dd7a598..5b4347a 100644
--- a/tcg/sparc/tcg-target.c
+++ b/tcg/sparc/tcg-target.c
@@ -194,6 +194,7 @@ static inline int tcg_target_const_match(tcg_target_long
val,
#define INSN_RS2(x) (x)
#define INSN_ASI(x) ((x) 5)
+#define INSN_IMM11(x) ((1 13) | ((x) 0x7ff))
#define INSN_IMM13(x) ((1 13) | ((x) 0x1fff))
#define INSN_OFF19(x) (((x) 2) 0x07)
#define INSN_OFF22(x) (((x) 2) 0x3f)
@@ -217,6 +218,9 @@ static inline int tcg_target_const_match(tcg_target_long
val,
#define COND_VC0xf
#define BA (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2))
+#define MOVCC_ICC (1 18)
+#define MOVCC_XCC (1 18 | 1 12)
+
#define ARITH_ADD (INSN_OP(2) | INSN_OP3(0x00))
#define ARITH_ADDCC (INSN_OP(2) | INSN_OP3(0x10))
#define ARITH_AND (INSN_OP(2) | INSN_OP3(0x01))
@@ -233,6 +237,7 @@ static inline int tcg_target_const_match(tcg_target_long
val,
#define ARITH_MULX (INSN_OP(2) | INSN_OP3(0x09))
#define ARITH_UDIVX (INSN_OP(2) | INSN_OP3(0x0d))
#define ARITH_SDIVX (INSN_OP(2) | INSN_OP3(0x2d))
+#define ARITH_MOVCC (INSN_OP(2) | INSN_OP3(0x2c))
#define SHIFT_SLL (INSN_OP(2) | INSN_OP3(0x25))
#define SHIFT_SRL (INSN_OP(2) | INSN_OP3(0x26))
@@ -580,6 +585,109 @@ static void tcg_out_brcond2_i32(TCGContext *s, int cond,
}
#endif
+static void tcg_out_setcond_i32(TCGContext *s, int cond, TCGArg ret,
+TCGArg c1, TCGArg c2, int c2const)
+{
+TCGArg t;
+
+/* For 32-bit comparisons, we can play games with ADDX/SUBX. */
+switch (cond) {
+case TCG_COND_EQ:
+case TCG_COND_NE:
+if (c2 != 0) {
+tcg_out_arithc(s, ret, c1, c2, c2const, ARITH_XOR);
+}
+c1 = TCG_REG_G0, c2 = ret, c2const = 0;
+cond = (cond == TCG_COND_EQ ? TCG_COND_LEU : TCG_COND_LTU);
+ break;
+
+case TCG_COND_GTU:
+case TCG_COND_GEU:
+if (c2const c2 != 0) {
+tcg_out_movi_imm13(s, TCG_REG_I5, c2);
+c2 = TCG_REG_I5;
+}
+t = c1, c1 = c2, c2 = t, c2const = 0;
+cond = tcg_swap_cond(cond);
+break;
+
+case TCG_COND_LTU:
+case TCG_COND_LEU:
+break;
+
+default:
+tcg_out_cmp(s, c1, c2, c2const);
+#if defined(__sparc_v9__) || defined(__sparc_v8plus__)
+tcg_out_movi_imm13(s, ret, 0);
+tcg_out32 (s, ARITH_MOVCC | INSN_RD(ret)
+ | INSN_RS1(tcg_cond_to_bcond[cond])
+ | MOVCC_ICC | INSN_IMM11(1));
+#else
+t = gen_new_label();
+tcg_out_branch_i32(s, INSN_COND(tcg_cond_to_bcond[cond], 1), t);
+tcg_out_movi_imm13(s, ret, 1);
+tcg_out_movi_imm13(s, ret, 0);
+tcg_out_label(s, t, (tcg_target_long)s-code_ptr);
+#endif
+return;
+}
+
+tcg_out_cmp(s, c1, c2, c2const);
+if (cond == TCG_COND_LTU) {
+tcg_out_arithi(s, ret, TCG_REG_G0, 0, ARITH_ADDX);
+} else {
+tcg_out_arithi(s, ret, TCG_REG_G0, -1, ARITH_SUBX);
+}
+}
+
+#if TCG_TARGET_REG_BITS == 64
+static void tcg_out_setcond_i64(TCGContext *s, int cond, TCGArg ret,
+TCGArg c1, TCGArg c2, int c2const)
+{
+tcg_out_cmp(s, c1, c2, c2const);
+tcg_out_movi_imm13(s, ret, 0);
+tcg_out32 (s, ARITH_MOVCC | INSN_RD(ret)
+ | INSN_RS1(tcg_cond_to_bcond[cond])
+ | MOVCC_XCC | INSN_IMM11(1));
+}
+#else
+static void tcg_out_setcond2_i32(TCGContext *s, int cond, TCGArg ret,
+ TCGArg al, TCGArg ah,
+ TCGArg bl, int blconst,
+ TCGArg bh, int bhconst)
+{
+int lab;
+
+switch (cond) {
+case TCG_COND_EQ:
+tcg_out_setcond_i32(s, TCG_COND_EQ, TCG_REG_I5, al, bl, blconst);
+tcg_out_setcond_i32(s, TCG_COND_EQ, ret, ah, bh, bhconst);
+tcg_out_arith(s, ret, ret, TCG_REG_I5, ARITH_AND);
+break;
+
+case TCG_COND_NE:
+tcg_out_setcond_i32(s, TCG_COND_NE, TCG_REG_I5, al, al, blconst);
+tcg_out_setcond_i32(s, TCG_COND_NE, ret, ah, bh, bhconst);
+tcg_out_arith(s, ret, ret, TCG_REG_I5, ARITH_OR);
+break;
+
+default:
+lab = gen_new_label();
+
+tcg_out_cmp(s, ah, bh, bhconst);
+tcg_out_branch_i32(s, INSN_COND(tcg_cond_to_bcond[cond], 1), lab);
+tcg_out_movi_imm13(s, ret, 1);
+
[Qemu-devel] Re: [PATCH 2/2] tcg-sparc: Implement setcond, setcond2.
On Tue, Feb 9, 2010 at 11:37 PM, Richard Henderson r...@twiddle.net wrote:
---
tcg/sparc/tcg-target.c | 126
1 files changed, 126 insertions(+), 0 deletions(-)
Something's wrong with the patch:
CCsparc-bsd-user/tcg/tcg.o
In file included from /src/qemu/tcg/tcg.c:158:
/src/qemu/tcg/sparc/tcg-target.c: In function `tcg_out_setcond_i32':
/src/qemu/tcg/sparc/tcg-target.c:623: warning: implicit declaration of
function `INSN_IMM11'
/src/qemu/tcg/sparc/tcg-target.c: At top level:
/src/qemu/tcg/sparc/tcg-target.c:1434: error: syntax error before '{' token
/src/qemu/tcg/sparc/tcg-target.c:1434: warning: initialization makes
integer from pointer without a cast
/src/qemu/tcg/sparc/tcg-target.c:1434: error: initializer element is
not computable at load time
/src/qemu/tcg/sparc/tcg-target.c:1434: error: (near initialization for
`sparc_op_defs[29].op')
/src/qemu/tcg/sparc/tcg-target.c:1434: warning: missing braces around
initializer
/src/qemu/tcg/sparc/tcg-target.c:1434: warning: (near initialization
for `sparc_op_defs[29].args_ct_str')
/src/qemu/tcg/sparc/tcg-target.c:1434: error: initializer element is
not constant
/src/qemu/tcg/sparc/tcg-target.c:1434: error: (near initialization for
`sparc_op_defs[29].args_ct_str')
/src/qemu/tcg/sparc/tcg-target.c:1434: error: initializer element is
not constant
/src/qemu/tcg/sparc/tcg-target.c:1434: error: (near initialization for
`sparc_op_defs[29]')
/src/qemu/tcg/sparc/tcg-target.c:1444: error: syntax error before '{' token
/src/qemu/tcg/tcg.c:68: warning: `tcg_op_defs' defined but not used
/src/qemu/tcg/tcg.c:76: warning: `tcg_target_available_regs' defined
but not used
/src/qemu/tcg/tcg.c:77: warning: `tcg_target_call_clobber_regs'
defined but not used
/src/qemu/tcg/tcg.c:127: warning: `tcg_out_label' defined but not used
/src/qemu/tcg/sparc/tcg-target.c:140: warning:
`target_parse_constraint' defined but not used
gmake[1]: *** [tcg/tcg.o] Error 1
